• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.10B
• /
• pp.1252-1257
• /
• 2011

In this paper, efficient functions for audio spectrum mapping with visible spectrum are proposed. Through mapping overall hearing frequency band with visible frequency band, emotional lighting might be possible. We propose a basic linear mapping function and non-linear mapping functions emphasizing specific audio frequency bands. For the algorithm implementation, spectrum analysis method and filter method are introduced. Especially, in this paper, a prototype LED lighting equipment using the digital filter method is implemented. The proposed lighting method can be applied to many LED lighting area using music.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.8
• /
• pp.23-30
• /
• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.3 s.35
• /
• pp.11-18
• /
• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.36T no.4
• /
• pp.71-81
• /
• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.1
• /
• pp.79-85
• /
• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.6
• /
• pp.672-677
• /
• 2016

Development of Internet has been successfully inspired with extensive deployment of the network technology and application. However, increases in Internet usage had caused a lot of traffic overload in these days. Thus, we need a continuous research and development on the network virtualization for effective resource allocation. In this paper, we propose a minimal cost virtual network mapping algorithm using Piecewise Linear Cost Function. We exploited an algorithm with Linear Programming and D-VINE for node mapping, and Shortest Path Algorithm based on linear programming solution is used for link mapping. In this way, we compared and analyzed the average cost for arrival rate of VN request with linear and tree structure. Simulation results show that the average cost of our algorithm shows better efficiency than ViNEyard.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.10b
• /
• pp.428-430
• /
• 2000

많은 산업 현장에서 서로 다른 표현 미디어 간에 칼라의 표현면에서 정확한 칼라 재생을 필요로 하고 있다. 본 논문에서는 확장 cusp 연결선을 이용한 새로운 색역 매핑에 관하여 논한다. 원본 색역내에 존재하는 칼라는 L*-C* 공간상에서 색 변환이 이루어지며 각 좌표에 대하여 동시에 변환이 이루어진다. 제안한 알고리즘에 의하여 기존의 색역 매핑 알고리즘보다 높은 채도(Chroma)값을 얻을 수 있었으며 재생이 이루어지는 색역의 이용도 또한 증가함을 실험을 통하여 보여준다.

• The KIPS Transactions:PartA
• /
• v.19A no.1
• /
• pp.17-22
• /
• 2012

The demand of high performance processor is soaring due to the extending of mobile and small electronic device market. CGRA(Coarse Grained Reconfigurable Architecture) is the processor satisfying both of performance and low-power demands and a great alternative of ASIC that can be reconfigured. This paper presents a novel low-power mapping algorithm that optimizes the number of used computation resource in the mapping phase by considering data transfer time. Compared with previous mapping algorithm, ours reduce energy consumption by up to 73%, and 56.4% on average.

• Journal of KIISE:Software and Applications
• /
• v.32 no.6
• /
• pp.554-569
• /
• 2005

In the semistructured distributed documents, it is very difficult to formalize and implement the query processing system due to the lack of structure and rule of the data. In order to precisely retrieve and process the heterogeneous semistructured documents, it is required to handle multiple mappings such as 1:1, 1:W and W:1 on an element simultaneously and to generate the schema from the distributed documents. In this paper, we have proposed an query processing algorithm for querying and answering on the heterogeneous semistructured data or documents over distributed systems and implemented with a metadata interface. The algorithm for generating local queries from the global query consists of mapping between g1oba1 and local nodes, data transformation according to the mapping types, path substitution, and resolving the heterogeneity among nodes on a global input query with metadata information. The mapping, transformation, and path substitution algorithms between the global schema and the local schemas have been implemented the metadata interface called DBXMI (for Distributed Documents XML Metadata Interface). The nodes with the same node name and different mapping or meanings is resolved by automatically extracting node identification information from the local schema automatically. The system uses Quilt as its XML query language. An experiment testing is reported over 3 different OEM model semistructured restaurant documents. The prototype system is developed under Windows system with Java and JavaCC compiler.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.4
• /
• pp.80-89
• /
• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.