• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.4
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• pp.709-717
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• 2012

The round reduction on block cipher is a fault injection attack in which an attacker inserts temporary errors in cryptographic devices and extracts a secret key by reducing the number of operational round. In this paper, we proposed an improved round reduction method to retrieve master keys by injecting a fault during operation of loop statement in the Triple DES. Using laser fault injection experiment, we also verified that the proposed attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented. Compared with previous attack method which is required 9 faulty-correct cipher text pairs and some exhaustive searches, the proposed one could extract three 56-bit secret keys with just 5 faulty cipher texts.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.91-100
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• 2011

The Triple Data Encryption Algorithm (Triple DES) is an international standard of block cipher, which composed of two encryption processes and one decryption process of DES to increase security level. In this paper, we proposed a Differential Fault Analysis (DFA) attack to retrieve secret keys using reduction of last round execution for each DES process in the Triple DES by fault injections. From the simulation result for the proposed attack method, we could extract three 56-bit secret keys using exhaustive search attack for $2^{24}$ candidate keys which are refined from about 9 faulty-correct cipher text pairs. Using laser fault injection experiment, we also verified that the proposed DFA attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.35-45
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• 2011

The Salsa20/12 stream cipher selected for the final eSTREAM portfolio has a better performance than software implementation of AES using an 8-bit microprocessor with restricted memory space, In the theoretical approach, the evaluation of exploitable timing vulnerability was 'none' and the complexity of side-channel analysis was 'low', but there is no literature of the practical result of power analysis attack. Thus we propose the correlation power analysis attack method and prove the feasibility of our proposed method by practical experiments, We used an 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement Salsa20/12 stream cipher without any countermeasures, and performed the experiments of power analysis based on Hamming weight model.

• Journal of the Society of Disaster Information
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• v.18 no.4
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• pp.699-705
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• 2022

Purpose: Sequence control is widely used by being applied to manufacturing, distribution, construction, and automation in the medical industry. With the development of the fourth industry, artificial intelligence convergence technology in the control field is becoming an important factor in the industry. In particular, it is required to evaluate the safety and innovation of facilities where microprocessors and artificial intelligence are fused to existing systems and develop reliable equipment, so it is intended to develop equipment for educational purposes and drive the development of the field. Method: The self-developed all-in-one artificial intelligence controller module is a device that combines artificial intelligence capabilities with existing sequence and PLC control circuits. As the performance evaluation items of this equipment, the recognition ability of motion, voice, text, color, etc. and the stability and reliability of the circuit were evaluated. Conclusion: After designing the sequence and PLC circuit, the performance evaluation items of the integrated integrated artificial intelligence controller module were all satisfied, and there was no problem in the safety and reliability of the circuit.

• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.197-202
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• 2023

This paper presents the design method and electrical characteristics of a high-efficiency power amplifier for a 50 Watts class repeater applied to a 5G system and used in in-building, subway, and tunnel. GaN was used for the termination transistor of the power amplifier designed here, and intermodulation signals were removed using DPD to satisfy linearity. In addition, in order to handle various requirements such as amplifier gain control and alarm processing required in the 5G system, the microprocessor is designed to exist inside the power amplifier. The amplifier manufactured to confirm the electrical performance of the power amplifier satisfying these conditions satisfied 46.5 dBm and the overall efficiency of the amplifier was 37%, and it was confirmed that it satisfied various alarm conditions and electrical characteristics required by telecommunication companies.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.28 no.3
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• pp.253-262
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• 1995

To develop a device for measuring fish freshness which could be move accurate and reliable than used freshness measuring systems. A new device based on digital circuit was designed using a microcomputer. The device was composed of a sensor part, 8096 microprocessor and a segment display. The effectiveness of device has been evaluated by the coefficient of correlation among the measured freshness stores such as electrical Q-value, K-value and amount of volatile basic nitrogen (VBN) of plaice, Paralichthys Olivaceus, during storage at $-3^{\circ}C,\;0^{\circ}C,\;5^{\circ}C,\;10^{\circ}C,\;and\;25^{\circ}C$. Q-values measured by a new device were more closely correlated with K-value (r=-0.978-\;-0.962,\;p<0.05) and VBN (r=-0.888-\;-0.988,\;p<0.05) in case of plaice meat. If more data would achieve using various fishes, this new designed device could be a valuable kit in fish market by its compact portability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8B
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• pp.509-520
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• 2007

In this paper, we propose a real-time sensor node platform that guarantees the real-time scheduling of periodic and aperiodic tasks through a multitask-based software decomposition technique. Since existing sensor networking operation systems available in literature are not capable of supporting the real-time scheduling of periodic and aperiodic tasks, the preemption of aperiodic task with high priority can block periodic tasks, and so periodic tasks are likely to miss their deadlines. This paper presents a comprehensive evaluation of how to structure periodic or aperiodic task decomposition in real-time sensor-networking platforms as regard to guaranteeing the deadlines of all the periodic tasks and aiming to providing aperiodic tasks with average good response time. A case study based on real system experiments is conducted to illustrate the application and efficiency of the multitask-based dynamic component execution environment in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. It shows that our periodic and aperiodic task decomposition technique yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.452-458
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• 2010

In case of an embedded system with computing resource restrictions such as system power and cpu, the overhead due to displaying data on the computer screen may have a significant influence on the system performance. This paper describes an initialization method for LCD-driving components such as an ARM Core, an LCD controller, and an SPI(serial peripheral interface). It also introduces a pixel display function and a panel display method using virtual screen for reducing the display overhead for an LN2440SBC system with an ARM9-based S3C2440A microprocessor. A virtual screen is a large space of computer memories allocated much larger than those needed for one-time display of an image. Displaying a specific region of a virtual screen is done by assigning it as a view-port region. Such a display is useful in an embedded system when concurrently running tasks produce and display their respective results on the screen; it is especially so when the execution result of each task is partially modified, instead of being totally modified, on its turn and displayed. If the tasks running on such a system divide and make efficient use of the region of the virtual screen, the display overhead can be minimized. For the performance comparison with and without using the virtual screen, two different images are displayed in turn and the amount of time consumed for their display is measured. The result shows that the display time of the former is about 5 times faster than that of the latter.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.54-68
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• 2011

As the prediction accuracy of conditional branch instruction is increased highly, the importance of prediction accuracy for unconditional branch instruction is also increased accordingly. Except the case of RAS(Return Address Stack) overflow, the prediction accuracy of function return address should be 100% theoretically. However, there exist some possibilities of miss-predictions for RAS return addresses, when miss-speculative execution paths are invalidated, in case of modern speculative microprocessor environments. In this paper, we propose the RAS rename technique to prevent RAS pollution, results in the reduction of RAS miss-prediction. We divide a RAS stack into a soft-stack and a hard-stack and we handle the instructions for speculative execution in the soft-stack. When some overwrites happen in the soft-stack, we move the soft-stack data into the hard-stack. In addition, we propose an enhanced version of RAS rename scheme. In simulation results, our solution provide 1/90 reduction of miss-prediction of function return address, results in up to 6.85% IPC improvement, compared to normal RAS method. Furthermore, it reduce miss-prediction ratio as 1/9, compared to previous technique.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.82-90
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• 2011

Multi-core system is becoming more general with development of microprocessors. Due to this change in performance improvement paradigm, switching conventional single thread applications with multi thread applications. Performance monitoring tools are used to optimize application performance because of complexity in development of multi thread applications. Conventional performance monitoring tools are focused on performance itself rather than user friendliness or real-time support. Real-time performance monitor identify the problem while multi-threaded applications should be performed as well as check real-time operating status of the application. So it can be used as an effective tool compared to non-real-time performance monitor that only with simple performance indicators to find the cause of the problem. In this paper, we propose RMPM(Real-time Multi-core Performance Monitor) which is real-time performance monitoring tool for multi-core system. Observation period is optimized by comparing relation between overhead due to performance evaluation period and accuracy. Our performance monitor shows not only amount of CPU usage of whole system, memory usage, network usage but also aspect of overhead distribution per thread of an application.