• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.9 s.112
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• pp.883-889
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• 2006

In this paper, parasitic resonance modes generated in a conductor backed coplanar wave guide(CBCPW) and stripline band pass filter(BPF) and the oscillation phenomena of a 40 GHz power amplifier module(PAM) are analyzed and several methods to suppress them are presented for low-temperature co-fired ceramic(LTCC) based millimeter-wave RF System-in-Package(SiP) applications. Parasitic rectangular wave guide(RWG) modes of the CBCPW structure are completely suppressed in the operation frequency band by decreasing the distance between its vias and by increasing the mode frequency. In the stripline structure, RWG resonance modes are clearly eliminated by removing some vias facing each other and by placing them diagonally. In the case of the 40 GHz PAM, in order to reduce a cross talk due to radiation that is generated from interconnection discontinuities, high isolation structures such as embedded DC bas lines and CPW signal lines are used and then the oscillated PAM is improved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.501-509
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• 2011

Software defined radio(SDR) has a goal that places the analog-to-digital converter(ADC) as near the antenna as possible. But current technique actually can't do analog-to-digital converting about RF band signals. So one method is studying that samples RF band signals to IF band. One of the ways Sub-Sampling technique can convert signals from RF band to IF band without oscillator. If Sub-Sampling technique is used, over 2 bands can convert signals from RF band to IF band. But due to the filter performance in RF band, it is possible to generate interference between signals that is converted in low frequency band. The effect degrades performance. In this paper, we propose one method that uses time division multiplexing(TDM) method as a solution to avoid interference between signals. By doing TDM and Sub-Sampling at the same time that method can get signals without large changes of structures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1028-1035
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• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.5
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• pp.391-399
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• 2005

Laser-generated ultrasonic inspection system is a non-contact scanning inspection device with high spatial resolution and wide bandwidth. The amplitude of laser-generated ultrasound is varied according to the energy of pulse laser and the surface conditions of an object where the CW measuring laser beam is pointing. In this paper, we correct the generating errors by measuring the energy of pulse laser beam and correct the measuring errors by extracting the gain information of laser interferometer at each time. h dynamic stabilizer is developed to stably scan on the surface of an object for an laser-generated ultrasonic inspection system. The developed system generates ultrasound after adaptively finding the maximum gain time of an laser interferometer and processes the signal in real time after digitization with high speed. In this paper, we describe hardware configuration and control algorithm to build a stable laser-generated ultrasonic inspection system. Also, we confirmed through experiments that the proposed correction method for the generating errors and measuring errors is effective to improve the performance of a system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.