• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.122-128
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• 2002

푸리에 변환을 사용하는 제1세대 웨이블릿은 정규화된 그리드에서만 적용되는 반면 리프팅 스킴을 사용한 제2세대 웨이블릿은 불규칙한 그리드를 처리할 수 있다. 본 논문에서는 제2세대 웨이블릿 생성 도구인 리프팅 스킴을 사용하여 압축된 적은 데이터를 사용한 근사치 영상을 생성하는 방법으로 부분 복원과 공간 복원 알고리즘과 리프팅 스킴을 이용한 에지 검출 기법이 제안되었다.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.19-26
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• 2005

The basis function of wavelet transform used in this paper is constructed by using lifting scheme, which is different from general wavelet transform. Lifting scheme is a new biorthogonal wavelet con-structing method, that does not use Fourier transform for constructing its basis function. In this paper, an image compression and reconstruction method using the lifting scheme was proposed. And this method improves data visualization by supporting a partial reconstruction and a local reconstruction. Approx- imations at various resolutions allow extracting various sizes of feature from an image or signal with a small amount of original information. An approximation with small size of scaling coefficients gives a brief outline of features at fast. Image compression and edge detection techniques provide good frame- works for data management and visualization in multimedia database.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1272-1277
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• 2010

Target detection and tracking wireless sensor network must have various signal processing ability. Wireless sensor nodes need to light weight signal processing algorithm because of energy constraints and communication bandwidth constraints. General signal processing algorithm of wireless sensor node consists of de-noising, received signal strength computation, feature extraction and signal compression. Wireless sensor network life-time and performance of target detection and classification depend on sensor node signal processing. In this paper, we propose energy efficient signal processing algorithm using wavelet transform. The proposed method estimates exact target position.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.