• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.11
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• pp.88-93
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• 2017

It is important to develop a simple method oftuning localized surface plasmon resonance(LSPR) properties, due to their numerous applications. In addition, the careful examination of the shape, size and combination of metal nanoparticles is useful for understanding the relation between the LSPR properties and metal nanostructures. This article describes the dependence of theLSPR properties on the arrays of metal nanoparticles obtained from a block copolymer(BCP) micellar thin film. Firstly, two different Au nanostructures, having a dot and ring shape, were fabricated using conventional block copolymer micelle lithography. Then, Ag was plated on the Au nanostructures through the silver mirror reaction technique to obtain Au/Ag bimetallic nanostructures. During the production of these metallic nanostructures, the processing factors, such as the pre-treatment by ethanol, silver mirror reaction time and removal or not of the BCP, were varied. Once the Au nanoparticles were synthesized, Ag was properly plated on the Au, providing two distinguishable characteristic plasmonic bands at around 525nm for Au and around 420nm for Ag, as confirmed bythe UV-vis measurements. However, when a small amount of Au seed nanoparticles, which accelerate the Ag plating speed,was formed by usinga block copolymer with a relatively highmolecular weight, all of the Au surfaces were fully covered by Ag during the silver mirror reaction, showing only the characteristic peak for Ag at around 420nm. The Ag plating technique on Au nanoparticles pre-synthesized from a block copolymer is useful to study the LSPR properties carefully.

• Korean Chemical Engineering Research
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• v.48 no.1
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• pp.33-38
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• 2010

A microfluidic system has been developed using biomaterial for the measurement of cupric ion concentration. The cell-membrane-mimicking bilayer lipid membrane(BLM)-coated silver electrode was used for the sensing of cupric ion concentration. The silver-supported BLM could increase its stability. A silver-supported bilayer lipid membrane(s-BLM) was easily obtained using its self-assembling characteristics by immersing silver wire into lipid(phosphatidylcholine; PC) solution and then dipping into aqueous KCl solution. These s-BLMs were used to determine the relationship between $Cu^{2+}$ concentration and current crossing s-BLM. Their relationship showed high linearity and reproducibility. The calibration curve was constructed to express the relationship between $Cu^{2+}$ concentration and current in the $Cu^{2+}$ concentration range of 10 and $130{\mu}M$. This calibration curve was used to measure $Cu^{2+}$ concentration in an unknown sample. Microfluidic system with s-BLM was made of PDMS(polydimethyl siloxane) using typical soft photolithography and molding technique. This integrated system has various functions such as activation of the silver surface without cutting silver wire, coating of BLM on silver surface, injection of KCl buffer solution, injection of $Cu^{2+}$ sample and measurement of $Cu^{2+}$ concentration in the sample.

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.99-101
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• 2000

The fabrication of the submicron size hole has been interesting due to the potential application of the near field optical sensor or liquid metal ion source. The 2 micron size dot array was photolithographically patterned. After formation of the V-groove shape by anisotropic KOH etching, dry oxidation at $1000^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have an etch-mask for dry etching. The reactive ion etching by the inductively coupled plasma (ICP) system was performed in order to etch ~90 nm $SiO_2$ layer at the bottom of the V-groove and to etch the Si at the bottom. The negative ion energy would enhance the anisotropic etching by the $Cl_2$ gas. After etching, the remaining thickness of the oxide on the Si(111) surface was measured to be ~130 nm by scanning electron microscopy. The etched Si aperture can be used for NSOM sensor.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.7-11
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• 2011

In this paper, we proposed a simple and high-yield printing process for source and drain electrodes of organic thin film transistor (OTFT). The surface energy of PVP (poly 4-vinylphenol) gate dielectric was decreased from 56 $mJ/m^2$ to 45 $mJ/m^2$ by adding fluoride of 3000ppm into it. Meanwhile the surface energy of source and drain (S/D) electrodes area on the PVP was increased to 87 $mJ/m^2$ by treating the areas, which was patterned by photolithography, with oxygen plasma, maximizing the surface energy difference from the other areas. A conductive polymer, G-PEDOT:PSS, was deposited on the S/D electrode areas by brushing painting process. With such a simple process we could obtain a high yield of above 90 % in $16{\times}16$ arrays of OTFTs. The performance of OTFTs with the fluoride-added PVP was similar to that of OTFTs with the ordinary PVP without fluoride, generating the mobility of 0.1 $cm^2/V.sec$, which was sufficient enough to drive electrophoretic display (EPD) sheet. The EPD panel employing the OTFT-backpane successfully demonstrated to display some patterns on it.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.275-280
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• 2005

We propose a new approach to greatly simplify the fabrication of conventional nanoimprint lithography (NIL) by combined nanoimprint and photolithography (CNP). We introduce a hybrid mask mold (HMM) made from UV transparent material with a UV-blocking Cr metal layer placed on top of the mold protrusions. We used a negative tone photo resist (PR) with higher selectivity to substrate the CNP process instead of the UV curable monomer and thermal plastic polymer that has been commonly used in NIL. Self-assembled monolayer (SAM) on HMM plays a reliable role for pattern transfer when the HMM is separated from the transfer layer. Hydrophilic $SiO_2$ thin film was deposited on all parts of the HMM, which improved the formation of SAM. This $SiO_2$ film made a sub-10nm formation without any pattern damage. In the CNP technique with HMM, the 'residual layer' of the PR was chemically removed by the conventional developing process. Thus, it was possible to simplify the process by eliminating the dry etching process, which was essential in the conventional NIL method.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.49-53
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• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.

• Journal of IKEEE
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• v.17 no.1
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• pp.71-76
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• 2013

AlGaN/GaN HEMTs (High electron mobility transistors) with narrow channel were fabricated and the effect of channel scaling on the device were investigated. The devices were fabricated using e-beam lithography to have same channel length of $1{\mu}m$ and various channel width from 0.5 to $9{\mu}m$. The sheet resistance of the channel was increased corresponding to the decrease of channel width and the increase was larger at the width of sub-${\mu}m$. The threshold voltage of the HEMT with $1.6{\mu}m$ and $9{\mu}m$ channel width was -2.85 V. The transistor showed a variation of 50 mV at the width of $0.9{\mu}m$ and the variation 350 mV at $0.5{\mu}m$. The transconductance of 250 mS/mm was decreased to 150 mS/mm corresponding to the decrease of channel width. Also, the gate leakage current of the HEMT decreased with channel width. But the degree of was reduced at the width of sub-${\mu}m$. It was thought that the variation of the electrical characteristics of the HEMT corresponding to the channel width came from the reduced Piezoelectric field of the AlGaN/GaN structure by the strain relief.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.73-73
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• 2000

안티퓨즈 소자는 프로그램 가능한 절연층의 상하 각각에 금속층이나 다결정 실리콘 등의 전도 가능한 전극으로 구성된다. 프로그램은 상하 전극간에 임계전압을 가했을 때 일어나게 되며 이때 절연층이 파괴되므로 비가역적이어서 재사용은 불가능하게 된다. 안티퓨즈 소자는 이러한 프로그램 특성으로 인하여 메모리 소자를 이용한 스위치 보다 속도나 집적도 면에서 우수하다. FPGAsdp 사용되는 안티퓨즈 소자는 집적도의 향상과 적정 절열파괴전압 구현을 위해 절연막의 두께를 감소시키는 것이 바람직하다. 그러나 두께나 감소될 경우 바닥전극의 hillock에 큰 영향을 받게 되며, 그로 인해 절연막의 두께를 감소시키는 것는 한계가 있는 것으로 보고되어 있다. 본 논문에서는 낮은 구동 전압에서 동작하고 안정된 on/pff 상태를 갖는 Al/TiO2-SiO2/Mo 형태의 안티퓨즈 소자를 제안하였다. 만들어진 antifuse cell은 0.6cm2 크기로 약 300개의 샘플을 제작하여 측정하였다. 비저항이 6-9 $\Omega$-cm인 P형의 실리콘 웨이퍼에 RF 마그네트론 스퍼터링(RF magnetron sputtering) 방법으로 하부전극인 Mo를 3000 증착하였다. SiO2는 안티퓨즈에서 완충막의 역할을 하며 구조적으로 antifuse cell을 완전히 감싸고 있는 형태로 제작되었다. 완충막 구조를 만들기 dln해 일반적인 포토리소그라피(Photo-lithography)작업을 거처 형성하였다. 형성된 hole의 크기는 5$mu extrm{m}$$\times$5$\mu\textrm{m}$ 이었다. 완충막이 형성된 기판위에 안티퓨즈 절연체인 SiO2를 PECVD 방식으로 100 증착하였다. 그 후 이중 절연막을 형성시키기 위해 LPCVD를 이용하여 TiO2를 150 증착시켰다. 상부 전극은 thermal evaporation 방식으로 Al을 250nm 증착하여Tejk. 하부전극으로 사용된 Mo 금속은 표면상태가 부드럽고 녹는점이 높은 매우 안정된 금속으로, 표면위에 제조된 SiO2의 특성을 매우 안정되게 유지시켰다. 제안된 안티푸즈는 이중절연막을 증착함으로서 전체적인 절연막의 두께를 증가시켜 바닥전극의 hillock의 영향을 적게 받아 안정성을 유지할 수 있도록 하였다. 또한, 두 절연막 사이의 계면 반응에 의해 SiO2 막을 약화시켜 절연막의 두께가 두꺼워졌음에도 기존의 SiO2 절연막의 절연 파괴 전압 및 누설 전류오 비교되는 특성을 가졌다. 이중막을 구성하고 있는 안티퓨즈의 ON-저항이 단일막과 비교해 비슷한 것을 볼 수 잇는데, 그 이유는 TiO2에 포함된 Ti가 필라멘트에 포함되어 있어 필라멘트의 저항을 감소시켰기 때문으로 사료된다. 결국 이중막을 구성시 ON-저항 증가에 의한 속도 저하 요인은 없다고 할 수 있다. 5V의 절연파괴 시간을 측정한느 TDDB 테스트 결과 1.1$\times$103 year로 기대수치인 수십 년보다 높아 제안된 안티퓨즈의 신뢰성을 확보 할 수 있었다. 제안된 안티퓨즈의 이중 절연막의 두께는 250 이고 프로그래밍 전압은 9.0V이고, 약 65$\Omega$의 on 저항을 얻을수 있었다.