• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.1-10
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• 2002

This paper presents the new template based human face recognition methods to improve the recognition performance against scale and in-plane rotation variations of face images. To enhance the recognition performance, the templates are generated by linear or nonlinear operation on multiple images including different scales and rotations of faces. As the invariant features to allow for scale and rotation variations of face images, we adopt the affine transformation, the log-polar mapping, and the log-polar image based FFT. The proposed recognition methods are evaluated in terms of the recognition rate and the processing time. Experimental results show that the proposed template based methods lead to higher recognition rate than the single image based one. The affine transformation based face recognition method shows marginally higher recognition rate than those of the log-polar mapping based method and the log-polar image based FFT, while, in the aspect of processing time, the log-polar mapping based method is the fastest one.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.4
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• pp.1-8
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• 2012

The NTFS journaling file($LogFile) is used to keep the file system clean in the event of a system crash or power failure. The operation on files leaves large amounts of information in the $LogFile. Despite the importance of a journal file as a forensic evidence repository, its structure is not well documented. The researchers used reverse engineering in order to gain a better understanding of the log record structures of address parts, and utilized the address for identifying object files to gain forensic information.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.524-530
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• 2015

A log is for text monitoring and perceiving the issues of a system during the development and operation of a program. Based on the log, system developers and operators can trace the cause of an issue. In the development phase, it is relatively simple for a log to be traced while there are only a small number of personnel uses of a system such as developers and testers. However, it is the difficult to trace a log when many people can use the system in the operation phase. In major cases, because a log cannot be tracked, even tracing is dropped. This study proposed a simplified tracing of a log during the system operation. Thus, the purpose is to create a log on the run time based on an ID/IP, using features provided by the Logback. It saves an ID/IP of the tracking user on a DB, and loads the user's ID/IP onto the memory to trace once WAS starts running. Before the online service operates, an Interceptor is executed to decide whether to load a log file, and then it generates the service requested by a certain user in a separate log file. The load is insignificant since the arithmetic operation occurs in a JVM, although every service must pass through the Interceptor to be executed.

• Journal of Korea Multimedia Society
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• v.6 no.5
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• pp.909-920
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• 2003

Nowadays, IT for CRM has been growing and developed rapidly. Typical techniques are statistical analysis tools, on-line multidimensional analytical processing (OLAP) tools, and data mining algorithms (such neural networks, decision trees, and association rules). Among customer data, web log data is very important and to use these data efficiently, applying OLAP technology to analyze multi-dimensionally. To make OLAP cube, we have to precalculate multidimensional summary results in order to get fast response. But as the number of dimensions and sparse cells increases, data explosion occurs seriously and the performance of OLAP decreases. In this paper, we presented why the web log data sparsity occurs and then what kinds of sparsity patterns generate in the two and t.he three dimensions for OLAP. Based on this research, we set up the multidimensional data models and query models for benchmark with each sparsity patterns. Finally, we evaluated the performance of three OLAP systems (MS SQL 2000 Analysis Service, Oracle Express and C-MOLAP).

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.183-187
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• 2023

양자 컴퓨터가 빠르게 발전됨에 따라 기존의 공개키 암호들이 기반하고 있는 난제인 소인수분해, 이산로그 문제를 다항 시간 안에 풀 수 있는 Shor 알고리즘에 의해 기존 암호의 보안 강도 약화 및 무력화 시기가 다가오고 있다. NIST에서는 양자 컴퓨터 시대에 대비하여 양자 컴퓨터가 등장하더라도 안전한 암호인 양자내성암호에 관한 공모전을 개최하였다. 양자 컴퓨터 환경에서 암호 분석을 통해 암호의 보안 강도를 확인할 수 있는데, 이를 위해서는 암호를 양자회로로 구현해야한다. 본 논문에서는 NIST PQC 공모전의 4 라운드 후보 알고리즘인 HQC (Hamming Quasi-Cyclic)의 PKE (Public Key Encryption) 버전에 대한 키 생성 및 인코딩 연산 중 핵심 역할을 하는 바이너리 필드 산술과shortened Reed-Solomon 코드의 인코딩 연산에 대한 최적화된 양자회로 구현을 제안하고, 이를 위해 필요한 자원을 추정한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.73-80
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• 2005

The Turbo decoders based on Log-MAP decoding algorithm inherently requires large amount of memory and intensive complexity of hardware due to iterative decoding, despite of excellent decoding efficiency. To decrease the large amount of memory and reduce hardware complexity, the result of previous research. And this paper design the Turbo decoder applicable to the 3G W-CDMA systems. Through the result of previous research, we decided 5-bits for the received data 6-bits for a priori information, and 7-bits for the quantization state metrics. The error correction term for $MAX^{*}$ operation which is the main function of Log-MAP decoding algorithm is implemented with very small hardware overhead. The proposed Turbo decoder is synthesized in $0.35\mu$m Hynix CMOS technology. The synthesized result for the Turbo decoder shows that it supports a maximum 9Mbps data rate, and a BER of $10^{-6}$ is achieved(Eb/No=1.0dB, 5 iterations, and the interleaver size $\geq$ 2000).

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.1
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• pp.35-45
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• 2007

The log data collected from mobile devices contains diverse meaningful and practical personal information. However, this information is usually ignored because of its limitation of memory capacity, computation power and analysis. We propose a novel method that detects landmarks of meaningful information for users by analyzing the log data in distributed modules to overcome the problems of mobile environment. The proposed method adopts Bayesian probabilistic approach to enhance the inference accuracy under the uncertain environments. The new cooperative modularization technique divides Bayesian network into modules to compute efficiently with limited resources. Experiments with artificial data and real data indicate that the result with artificial data is amount to about 84% precision rate and about 76% recall rate, and that including partial matching with real data is about 89% hitting rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.