• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.73-77
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• 2007

In this paper, we propose a VLSI architecture of an LMS filter based on a Cyclo-static scheduler for fast computation of LMS filteing algorithm which is widely used in adptive filtering area. This process is composed of two steps: scheduling and circuit synthesis. The scheduling step accepts a fully specified flow graph(FSFG) as an input, and generates an optimal Cyclo-static schedule in the sense of the sampling rate, the number of processors, and the input-output delay. Then the generated schedule is transformed so that the number of communication edges between the processors. The circuit synthesis part translates the modified schedule into a complete circuit diagram by performing resource allocations. The VLSI layout generation can be performed easily by an existing silicon compiler.

• Journal of the Institute of Convergence Signal Processing
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• v.17 no.1
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• pp.26-31
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• 2016

In this paper, we propose an image quality evaluation system for compact camera module and assess the effect of optical performance improvement for proposed anti-halation disk in small lens. We develop a image quality evaluation system for quality estimation of camera module image. And we also develop a program to control register in image signal processor. Finally the resolution, brightness, and color reproduction performances were evaluated image quality comparison between conventional and proposed camera module using developed quality evaluation system and ISP register control program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.664-672
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• 2002

This paper analyzes a sequential estimator with flexible structure for rapid acquisition of the m-sequence signals. If the received PN chips stored in the estimator's internal registers as initial loading values include one error, this chip with error can be corrected through multiple local PN code generators to achieve high-speed acquisition performance. Hamming distance between regenerated local PN codes from the proposed system and received PN code is compared with given threshold to choose a possible correct path and to declare success of the code acquisition. Using signal flow graph, average acquisition time that depends on detection and false alarm probability is calculated. By modifying generally used matched filter structure for PN code acquisition, the proposed system provides flexible structure and rapid acquisition process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1175-1182
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• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of Digital Contents Society
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• v.17 no.3
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• pp.173-180
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• 2016

In this paper, a design of transceiver module for real-time wire and wireless robust integrated security system to solve the problem of conventional security system and its transceiver module is proposed. The presented robust integrated security system is designed with RF control unit and wireless transceiver module. A RF controller in transceiver module works as a low-power RF transceiver system. It is designed to use specific bandwidth stored in registers and manipulate RF power of transceiver by accessing the random values of registers. Operation algorithm for RF transceiver module is also presented. The designed transceiver module and the operation algorithm are implemented and verified by experiments.

• Proceedings of the CALSEC Conference
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• 2003.09a
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• pp.115-120
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• 2003

To execute business collaborations, the business process specification is required and it is generated from the business process model. ebXML, which is the XML-based B2B standard framework for organizations over the Internet, recommends process analyst and modeler to use UN/CEFACT Modeling Methodology for modeling. All the artifacts of the modeling and transformed results between different business models may be registered in the business library for the share and re-use. In this paper, we implement the business process modeler including built-in registry client. It provides not only modeling the business process but also generating the specifications, exporting the metadata about the business model, and registering in the business library.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.220-227
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• 2002

An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.17-22
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• 2004

We developed a new ANGLED display driving method which used both amplitude and pulse width modulation. For pulse width modulation, we divided a picture frame time into S sub-frames. For amplitude modulation, we used three OLED luminance(or current) levels which were controlled by TFT's gate voltages. By combining these two modulation methods, we obtained 35(=243) grey levels. And we designed a new data electrode driving circuit block with two shift registers without using DAC's. To verify the feasibility, we simulated the key circuit components by HSpice with TFT parameters extracted from current-voltage characteristics of 6${\mu}{\textrm}{m}$ channel length polysilicon TFT's. From the simulation results, we found that 320${\times}$240, dual scan, 243 grey level AMOLED display can be designed with this method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.623-630
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• 2016

Heterogeneous IoT devices must satisfy a certain level of security for mutual connections and communications. However, a performance degradation of cryptographic algorithms in resource constrained devices is inevitable and so an optimization or efficient implementation method is necessary. In this paper, we study an efficient implementation method for rotation operations regarding registers for running ARX lightweight block ciphers. In a practical sense, we investigate the performance of modified rotation operations through experiments using real experiment devices. We show the improved performance of modified rotation operations and discover the significant difference in measured performance between simulations and real experiments, particularly for 16-bit MSP microcontrollers.

• The KIPS Transactions:PartA
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• v.8A no.1
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• pp.27-35
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• 2001

This paper presents the assignment motion algorithm unrestricted for code optimization computationally. So, this algorithm is suppressed the unnecessary code motion in order to avoid the superfluous register pressure, we propose the assignment motion algorithm added to the final optimization phase. This paper improves an ambiguous meaning of the predicated. For mixing the basic block level analysis with the instruction level analysis, an ambiguity occurred in knoop’s algorithm. Also, we eliminate an ambiguity of it. Our proposal algorithm improves the runtime efficiency of a program by avoiding the unnecessary recomputations and reexecutions of expressions and assignment statements.