• Title/Summary/Keyword: 레이아웃 알고리즘

Search Result 75, Processing Time 0.028 seconds

A Study on Product Move Operation Optimal Path Based on Business Supporting System & Spatial Information (업무지원 시스템 및 공간정보 기반의 제품 이동 작업 경로 최적화 기법 연구)

  • Sung-il Park;Ik-Soo choi
    • Proceedings of the Korean Society of Computer Information Conference
    • /
    • 2023.07a
    • /
    • pp.555-556
    • /
    • 2023
  • 본 논문에서는 제조/물류 기업 등 제품(물품) 이동 작업 시 효율적인 경로 제공을 위한 경로 최적화 기법을 제안한다. 이 기법은 업무지원 시스템(MES, ERP, WMS 등)이 구축되어있는 기업을 대상으로 공간정보와 업무지원 시스템에 저장되는 제품 데이터를 기준 정보로 하며, 다익스트라(Dijkstra), 개미 집단 알고리즘(Ant Colony Algorithm, ACO)등 경로 탐색 알고리즘을 적용하여 문제를 해결하고자 한다. 공간정보는 공장(현장)의 레이아웃(Layout)과 제품이 적재/출하되는 렉(Rack) 등의 위치 정보가 포함되고, 업무지원 시스템에서 제품의 현재 위치, 공정 상태, 등록 시간, 제품 크기 등을 사용한다. 제안하는 기법은 상기 기준 정보를 경로 탐색 알고리즘에 적용하여 적재/출하, 공정 이동, 보관 장소 변경 등 제품의 위치가 변경되는 경우에 경로를 최적화할 수 있는 기법을 제안한다. 제품 이동 작업은 대부분 노동력에 의존하는 작업으로 경로 최적화 기법을 제안함으로써, 인력 비용 감소와 향후 로봇 기반의 제품 이동 작업에도 적용하여 자동화된 작업효과를 가져다 줄 것으로 기대한다.

  • PDF

Development of Web Accessibility Evaluation Algorithm-Based upon Table Element (웹 접근성 평가 알고리즘 개발-Table 요소 중심으로)

  • Park, Seong-Je;Kim, Jong-Weon
    • Journal of Korea Society of Industrial Information Systems
    • /
    • v.18 no.4
    • /
    • pp.81-87
    • /
    • 2013
  • Due to the development of IT technologies and the Internet penetration, the importance of Web accessibility has greatly increased and accordingly been studied a lot. This study noticed that the current evaluation algorithm for "Table Elements," which are used for data and layout tables, has many problems. Based on the Web Accessibility Guidelines, this study presents an improved evaluation algorithm for "Table Elements" and verifies its validity.

A Study on Computer Aided VLSI System Design (VLSI System CAD에 관한 연구)

  • 박진수
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.8 no.1
    • /
    • pp.30-37
    • /
    • 1983
  • In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.

  • PDF

A ASIC design of the Improved PN Code Acquisition System for DS/CDMA (DS-CDMA용 개선된 PN 코드 포착 시스템의 ASIC 설계)

  • Jo, Byeong-Rok;Park, Jong-U
    • The KIPS Transactions:PartD
    • /
    • v.9D no.1
    • /
    • pp.161-166
    • /
    • 2002
  • The existing method in PN code acquisition process have a problem in PN code acquisition time because PN code searching is accomplished in one epoch. In this paper, we propose algorithm that can reduce PN code acquisition time because PN code searching is accomplished in each other two epoches. The designed ASIC chip using proposed algorithm confirmed that the area (the number of gates) increase more than existing method in PN code acquisition, but the performance of PN code acquisition is better than existing method.

Implementation of pattern generator for efficient IDDQ test generation in CMOS VLSI (CMOS VLSI의 효율적인 IDDQ 테스트 생성을 위한 패턴 생성기의 구현)

  • Bae, Seong Hwan;Kim, Gwan Ung;Jeon, Byeong Sil
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.38 no.4
    • /
    • pp.50-50
    • /
    • 2001
  • IDDQ 테스트는 CMOS VLSI 회로에서 발생 가능한 여러 종류의 물리적 결함을 효율적으로 검출 할 수 있는 테스트 방식이다. 본 논문에서는 CMOS에서 발생 빈도가 가장 높은 합선고장을 효과적으로 검출할 수 있는 IDDQ 테스트 알고리즘을 이용하여 패턴 생성기를 개발하였다. 고려한 합선고장 모델은 회로의 레이아웃 정보에 의존하지 않으며, 내부노드 혹은 외부노드에 한정시킨 합선고장이 아닌 테스트 대상회로의 모든 노드에서 발생 가능한 단락이다. 구현된 테스트 패턴 생성기는 O(n2)의 복잡도를 갖는 합선고장과 전압 테스트 방식에 비해 상대적으로 느린 IDDQ 테스트를 위해서 새롭게 제안한 이웃 조사 알고리즘과 고장 collapsing 알고리즘을 이용하여, 빠른 고장 시뮬레이션 시간과 높은 고장 검출율을 유지하면서 적은 수의 테스트 패턴 생성이 가능하다. ISCAS 벤치마크 회로의 모의실험을 통하여 기존의 다른 방식보다 우수한 성능을 보였다.

Polygon Resizing Algorithm for Mask Artwork Processing and Layout Verification (마스크 아트웍 처리 및 레이아웃 검증을 위한 다각형 정형 알고리즘)

  • 정자춘;이철동;유영욱
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.24 no.6
    • /
    • pp.1087-1094
    • /
    • 1987
  • In this paper, we describe about polygon resizing porblem where the given polygons are expanded or shrunk in two dimensional plane. First, the definition of polygon resizing and it's problems are given, then the enhanced XY method is proposed: the polygon resizing can be completed in one directional sweep of plane only, usisng enhanced plane sweep method. The time complexity is 0(n log n), and space complexity 0(\ulcorner), where n is the number of verties of polygons. The applications of polygon resizing to the mask artwork processing and layout verification are discussed.

  • PDF

Development of a Rectangle-based Layout Object Extraction Algorithm (직사각형을 기반으로 하는 레이아웃 개체추출 알고리즘)

  • 최용석;천익재;김보관
    • Proceedings of the IEEK Conference
    • /
    • 2001.06b
    • /
    • pp.113-116
    • /
    • 2001
  • In this paper we present a new hierarchical layout object extraction algorithm, which is based on rectangles rather than edges. The original layout data is modeled as instances connected by wires. Each polygon shape is divided into a set of rectangles and the instances and wires are extracted and recognized from those rectangles together with their connection and size information. We have applied the algorithm to actual layouts. Experiments on several standard cell library demonstrate the effectiveness of the algorithm.

  • PDF

A function-based abstraction method for visualizing the large scale of protein-protein interaction relationships (대용량 단백질 상호관계의 시각화를 위한 기능기반 추상화 방법)

  • 김대희;최재훈;정재영;박선희
    • Proceedings of the Korean Information Science Society Conference
    • /
    • 2003.10b
    • /
    • pp.793-795
    • /
    • 2003
  • 이 논문은 대용량 단백질 상호작용의 관계를 효과적으로 시각화하기 위해 단백질이 가지고 있는 기능에 기반한 추상화 방법을 제안한다. 제안하는 방법은 FDP(force-directed placement) 알고리즘에 기반을 두고 있지만 다중 레벨 처리를 위해 기능에 기반한 추상화 방법과 확장을 사용한다는 점에서 차이점을 나타낸다. 제안하는 그래프 레이아웃 방법은 추상화, 위치화, 확장의 3부분으로 구성되어 있으며 특히 추상화 부분은 다중 레벨 처리를 포함한다.

  • PDF

Social graph visualization techniques for public data (공공데이터에 적합한 다양한 소셜 그래프 비주얼라이제이션 알고리즘 제안)

  • Lee, Manjai;On, Byung-Won
    • Journal of the HCI Society of Korea
    • /
    • v.10 no.1
    • /
    • pp.5-17
    • /
    • 2015
  • Nowadays various public data have been serviced to the public. Through the opening of public data, the transparency and effectiveness of public policy developed by governments are increased and users can lead to the growth of industry related to public data. Since end-users of using public data are citizens, it is very important for everyone to figure out the meaning of public data using proper visualization techniques. In this work, to indicate the significance of widespread public data, we consider UN voting record as public data in which many people may be interested. In general, it has high utilization value by diplomatic and educational purposes, and is available in public. If we use proper data mining and visualization algorithms, we can get an insight regarding the voting patterns of UN members. To visualize, it is necessary to measure the voting similarity values among UN members and then a social graph is created by the similarity values. Next, using a graph layout algorithm, the social graph is rendered on the screen. If we use the existing method for visualizing the social graph, it is hard to understand the meaning of the social graph because the graph is usually dense. To improve the weak point of the existing social graph visualization, we propose Friend-Matching, Friend-Rival Matching, and Bubble Heap algorithms in this paper. We also validate that our proposed algorithms can improve the quality of visualizing social graphs displayed by the existing method. Finally, our prototype system has been released in http://datalab.kunsan.ac.kr/politiz/un/. Please, see if it is useful in the aspect of public data utilization.

Design of Dynamic Time Warp Element for Speech Recognition (음성인식을 위한 Dynamic Time Warp 소자의 설계)

  • 최규훈;김종민
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.19 no.3
    • /
    • pp.543-552
    • /
    • 1994
  • Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

  • PDF