• 한국정보교육학회:학술대회논문집
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• 2006.08a
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• pp.151-159
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• 2006

in this paper, by analyzing the conditions in which the user's usability is positively effected, I made an attempt to present consideration to make in the development of the prototype.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.543-552
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• 1994

Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.639-647
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• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.714-718
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• 1997

제품 설계에 있어 설계 기간의 단축과 설계변경에의 효과적인 대응은 매우 중요하다. 본 논문에서는 공학설 계의 한 방법인 구성설계 방법론을 이용하여 제품을 구성하는 부품 사양을 결정하고, 그에 따른 전체 제품의 조림 레이아웃을 파라메트릭 기법을 적용하여 CAD시스템상에 가시화하는 전문가시스템을 구축하였는데,이 시스템은 제품 성계에서 전체적인 품질이 결정되는 초기설계 단계에 대하여 형상 표현에 중점을 두고 구성 되었다.

• Journal of Advanced Marine Engineering and Technology
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• v.34 no.6
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• pp.806-815
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• 2010

Gear trains are combined with the planetary gear units and helical gear units. It is known that the combination type is decisive to the system performances of the transmissions. In this paper, within the commonly used range of the design requirements for medium and large scaled (1~8 MW) wind turbines, the transmission characteristics of the typical layouts of the gear train are investigated. According to the international standard by ANSI/AGMA/AWEA 6006-A03, the gear boxes are basically designed and compared with respect to the system lifes of 99% reliability, total weight, the power densities, overall diameter/length and the maximum stresses of the gear teeth. With these comparison works, the characteristics of the layouts of gear trains are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.648-658
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• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.690-692
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• 2009

PLL은 위상주파수검출기(PFD), 차지펌프(Charge Pump), 루프필터(Loop Filter), 전압제어발진기(VCO), Divider로 구성하고 있는데 본 논문에서는 설계된 차지펌프 PLL을 시뮬레이션을 해보고 그 결과를 정리하고 레이아웃(layout)까지 하였다. 차지펌프 설계에 있어서 전류 부정합, 전하 공유, 전하주입, 누설 전류등을 고려할 필요가 있다. 설계된 차지펌프는 전류 부정합을 감소시키기 위해 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, spurs를 억제할 수 있도록 설계되였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 specter로 시뮬레이션 하였으며, virtuso2로 레이아웃 하였다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.6 s.177
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• pp.1379-1389
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• 2000

In this study, a design process of robotic cell is presented. This paper focuses only on the automation of workpiece handling with robot. The presented design process enables us to analyze effectiv ely the original production system and to redesign it as an optimum production system with robots. An original production system is analyzed with respect to its economical and technological requirements for automation. If automation of the given production system is feasible, the conceptual design for automation is firstly derived. Next, the detail design is derived for the optimum conceptual design. Finally, an optimum system solution is determined after the economical and technical evaluation of all the derived detail designs. The all specifications of each element of the redesigned production system and its layout are determined at the detail design phase. This paper shows a low cost supporting tool for layout design of robotic cell with SCARA type robots.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.