• The Journal of the Convergence on Culture Technology
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• v.10 no.2
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• pp.517-524
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• 2024

This study aims to train and implement a deep learning model for the fusion of website creation and artificial intelligence, in the era known as the AI revolution following the launch of the ChatGPT service. The deep learning model was trained using 3,000 collected web page images, processed based on a system of component and layout classification. This process was divided into three stages. First, prior research on AI models was reviewed to select the most appropriate algorithm for the model we intended to implement. Second, suitable web page and paragraph images were collected, categorized, and processed. Third, the deep learning model was trained, and a serving interface was integrated to verify the actual outcomes of the model. This implemented model will be used to detect multiple paragraphs on a web page, analyzing the number of lines, elements, and features in each paragraph, and deriving meaningful data based on the classification system. This process is expected to evolve, enabling more precise analysis of web pages. Furthermore, it is anticipated that the development of precise analysis techniques will lay the groundwork for research into AI's capability to automatically generate perfect web pages.

• Journal of Korean Tunnelling and Underground Space Association
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• v.21 no.5
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• pp.587-609
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• 2019

Short-and long-term stabilities of bentonite, favored material as buffer in geological repositories for high-level waste were reviewed in this paper in addition to alternative design concepts of buffer to mitigate the thermal load from decay heat of SF (Spent Fuel) and further increase the disposal efficiency. It is generally reported that the irreversible changes in structure, hydraulic behavior, and swelling capacity are produced due to temperature increase and vapor flow between $150{\sim}250^{\circ}C$. Provided that the maximum temperature of bentonite is less than $150^{\circ}C$, however, the effects of temperature on the material, structural, and mineralogical stability seems to be minor. The maximum temperature in disposal system will constrain and determine the amount of waste to be disposed per unit area and be regarded as an important design parameter influencing the availability of disposal site. Thus, it is necessary to identify the effects of high temperature on the performance of buffer and allow for the thermal constraint greater than $100^{\circ}C$. In addition, the development of high-performance EBS (Engineered Barrier System) such as composite bentonite buffer mixed with graphite or silica and multi-layered buffer (i.e., highly thermal-conductive layer or insulating layer) should be taken into account to enhance the disposal efficiency in parallel with the development of multilayer repository. This will contribute to increase of reliability and securing the acceptance of the people with regard to a high-level waste disposal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Korean Institute of Landscape Architecture
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• v.49 no.5
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• pp.97-111
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• 2021

The purpose of this study was to analyze commemoration characteristics of the United States of America, the Commonwealth, and Germany through representative 14 military cemeteries of World war II in Western Europe. Based on the commemoration characteristics such as spacial characteristic, commemorative elements, and graves and headstone, the commemoration culture among U.S., the Commonwealth. and Germany were studied comparatively. The results are as follows. First, taking geometrical form with mainly square type, rarely circle and spiral patterned, most cemeteries were structured spatial central axis with symmetry, those cemeteries were styled neoclassical, but some of the U.S. cemeteries were modernistic, connecting spaces organically with curved line layout. Second, chapel, the wall of missing, the wall of battle map, and sculpture in the U.S military cemeteries, and 'the cross of sacrifice' and 'the stone of remembrance' as classical monument in the Commonwealth war cemeteries were commonly applied standardized commemorative elements, but commemorative monuments in German military cemeteries were restricted except monumental cross. Third, the symbolic cross of christianism was used all cemeteries to console and cherish the soul of soldiers, specially the Latin crosses in the U.S military cemeteries delivered political message as the american martyr for Western Europe and also the power of the U.S., but the cross in German and the Commonwealth war cemeteries were basically cherish and comfort individual spirit. Fourth, showing the power of victory with national patriotism, the U.S. strongly represented christianism and liberal democracy against communism, the Commonwealth showed imperialistic style, and German military cemeteries were quietly appeared as traditional style forwarding reconciliation and peace. This study suggest the war cemeteries have national identity with typical form and symbolic aesthetics. Further study will be required to materialize sublime commemoration in national cemeteries and to form advanced commemorative culture in Korea.