• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.53-58
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• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.

• The Transactions of the Korea Information Processing Society
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• v.6 no.10
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• pp.2809-2815
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• 1999

Level set, and active contour(snakes) models are extensively used for image segmentation or shape extraction in computer vision. Snakes utilize the energy minimization concepts, and level set is based on the curve evolution in order to extract contours from image data. In general, these two models have their own drawbacks. For instance, snake acts pooly unless it is placed close to the wanted shape boundary, and it has difficult problem when image has multiple objects to be extracted. But, level set method is free of initial curve position problem, and has ability to handle topology of multiple objects. Nevertheless, level set method requires much more calculation time compared to snake model. In this paper, we use good points of two described models and also apply multi resolution algorithm in order to speed up the process without decreasing the performance of the shape extraction.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.16-28
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• 2000

In this paper, we implemented by describing a pipeline processor using a HDL in functional level, simulated and verified it's operation. When simulating a implemented processor. We first specify assembly instruction that is Performed in the processor. entered by programming using the instruction sets at the experimental framework. Thus, the procedure that is presented in this paper can easily identify and verify the purpose for implementation and operation of a system by using test vector. Also, it was possible that exactly simulate a system. The method was comfortable that document a system operation to implement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.5
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• pp.13-20
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• 2008

Although digital hearing aid algorithms have been developed to compensate hearing loss and to help hearing impaired people to communicate with others, digital hearing aid user still complain about difficulty of hearing the speech. The reason could be the quality of speech through digital hearing aid is insufficient to understand the speech caused by feedback, residual noise and etc. And another thing is masking effect among formants that makes sound quality low. In this study, we measured the masking characteristics of normal listeners and hearing impaired listeners having presbyacusis to confirm masking effect in speech itself. The experiment is composed of 5 tests; pure tone test, speech reception threshold (SRT) test, word recognition score (WRS) test, puretone masking test and speech masking test. In speech masking test, there are 25 speeches in each speech set. And log likelihood ratio (LLR) is introduced to evaluate the distortion of each speech objectively. As a result, the speech perception became lower by increasing the quantity of formant enhancement. And each enhanced speech in a speech set has statistically similar LLR, however speech perception is not. It means that acoustic masking effect rather than distortion influences speech perception. In actuality, according to the result of frequency analysis of the speech that people can not answer correctly, level difference between first formant and second formant is about 35dB, and it is similar to result of pure tone masking test(normal hearing subject:36.36dB, hearing impaired subject:32.86dB). Characteristics of masking effect is not similar between normal listeners and hearing impaired listeners. So it is required to check the characteristics of masking effect before wearing a hearing aid and to apply this characteristics to fitting.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.40 no.1
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• pp.15-22
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• 2022

In order to improve the accuracy of the deep learning object detection technique, the effect of magnification rate conditions and seasonal factors on detection accuracy in aerial photographs and drone images was analyzed through experiments. Among the deep learning object detection techniques, Mask R-CNN, which shows fast learning speed and high accuracy, was used to detect the vehicle to be detected in pixel units. Through Seoul's aerial photo service, learning images were captured at different screen magnifications, and the accuracy was analyzed by learning each. According to the experimental results, the higher the magnification level, the higher the mAP average to 60%, 67%, and 75%. When the magnification rates of train and test data of the data set were alternately arranged, low magnification data was arranged as train data, and high magnification data was arranged as test data, showing a difference of more than 20% compared to the opposite case. And in the case of drone images with a seasonal difference with a time difference of 4 months, the results of learning the image data at the same period showed high accuracy with an average of 93%, confirming that seasonal differences also affect learning.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.5
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• pp.537-543
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• 2012

In this study, we experimentally investigate a noise mechanism related to the machining accuracy of the reducer in the driving state. We fabricate a planetary reducer and four types of gears for use in the planetary reducer. We use signal analysis to determine the noise and vibration of the reducer at different motor speeds; the motor speed is increased from 0 rpm to the maximum speed in a stepwise manner. In addition, we obtain the sound level by using a sound level meter. The machining accuracy of gears is evaluated by public organizations, Korea Testing Laboratory (KTL), on the basis of the Japanese Industrial Standard (JIS). We analyze and compare the results with the noise and vibration of the reducer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1462-1468
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• 2022

Among the data used for the diagnosis of calf disease, feces play an important role in disease diagnosis. In the image of calf feces, the health status can be known by the shape, color, and texture. For the fecal image that can identify the health status, data of 207 normal calves and 158 calves with diarrhea were pre-processed according to fecal status and used. In this paper, images of fecal variables are detected among the collected calf data and images are trained by applying GLCM-CNN, which combines the properties of CNN and GLCM, on a dataset containing disease symptoms using convolutional network technology. There was a significant difference between CNN's 89.9% accuracy and GLCM-CNN, which showed 91.7% accuracy, and GLCM-CNN showed a high accuracy of 1.8%.