• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3435-3446
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• 1999

The application of Computer Aided Design (CAD) tool to rehabilitative surgery of the hand is a new field of endeavor. It is considered that there are currently no existing systems designed to assist the orthopedic surgeon in planning complex procedures such as tendon transfer operations. Most tendon transfer operations are performed by surgeons on the basis of knowledge and experience gained through years of practice. However, with the help of this computer graphics-based CAD tool for planning tendon paths, the planning and the evaluation for the best operation on patients' hands also may be possible. The purpose of this study was to model kinematically the structure of the hand and design a prototype tendon path planning tool with a standard computer graphics library, in order for surgeons to perform tendon transfer surgery more objectively and quantitatively.

• Annual Conference of KIPS
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• 2015.10a
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• pp.956-958
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• 2015

소프트웨어 개발 프로세스 진행 중 산출 문서를 제작에 많은 시간적 비용이 필요하다. 또한 빈번한 데이터 또는 템플릿이 변경으로 수정 비용이 추가적으로 발생된다. 만일 개발 프로세스 과정에 PAL을 적용하여 자동 문서 생성이 가능하여 시간적 비용을 감소시킬 수 있다. 이를 위해, XML와 XSLT 기반의 PAL 엔진 설계 방법을 제안한다. 또한 표준 언어를 사용함으로써, 첫째로 시스템 관리자가 쉽게 문서 템플릿을 수정 가능하며, 둘째로 기존 시스템에 빠르게 적용 할 수 있다. 추가로 HTML 코드로 문서를 생성하여 일반 웹 브라우저에서 결과 문서 출력이 가능하다.

• Annual Conference of KIPS
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• 2015.10a
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• pp.223-226
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• 2015

최근 클라우드를 지원하는 Xen 가상화 환경에서 HPC를 구현하는 서비스의 수가 증가하고 있다. 따라서 SMP기반의 병렬컴퓨팅 구현을 위한 표준 라이브러리인 OpenMP 연산효율의 중요성이 높아지고 있다. 본 논문에서는 Xen 가상화 기반 OpenMP 환경에서 CPU Pinning 적용 여부에 따라 다양한 태스크 스케줄링의 성능 변화를 측정하기 위한 실험을 수행하였다. 실험결과, CPU Pinning을 적용했을 시정적 스케줄링은 3.7%, 동적 스케줄링은 3.4%, 태스크 지시자 스케줄링은 3.8%의 성능 향상을 보였다. 이러한 결과는 Xen 가상화 환경에서 효율적인 병렬 컴퓨팅 기법 설계를 위한 방향을 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.11a
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• pp.170-173
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• 2018

최근 360 비디오를 지원하는 가상현실 시스템에 대한 수요가 높아지면서, 사용자의 편의를 위해 다양한 방법이 제안되고 있다. Moving Picture Experts Group (MPEG) 에서는 제한적인 사용자 경험을 제공하는 3DoF 를 넘어 3DoF+, 6DoF 표준을 진행하고 있고, 이에 따른 많은 연구도 활발히 진행되고 있다. 사용자가 앉아있는 상태에서 머리의 움직임에 따라 제한적인 자유도를 제공하는 3DoF+ 시스템은 여러 고해상도의 360 비디오 전송을 요구하여 네트워크 대역폭에 상당한 부담을 준다. 본 논문은 3DoF+ 360 비디오 전송 시 대역폭의 효율적 사용을 위한 비트레이트 절감 방안을 제안한다. 이를 위해, 본 논문은 360 비디오의 프로젝션을 변경하여 해상도를 줄이면서도 정보 손실을 최소화할 수 있는 방법을 제시하고 결과를 설명한다. 프로젝션 변경을 위해 360 라이브러리를 사용하였고, 인코딩과 디코딩 시 효율 측정을 위해 HEVC Test Model (HM)을 사용하였다. 최종적으로 구현된 시스템은 360 비디오를 최적의 프로젝션으로 변환 후 인코딩, 디코딩을 거치고 다시 360 비디오로 변환하는 과정을 지원한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.41-56
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• 2007

In this paper, we propose a specification-based intrusion detection system for WIPI(Wireless Internet Platform for Interoperability). In proposing the system, we focused on providing lightweight code, supporting multiple languages and hardware independence. The proposed system is based on an algorithm which detects an intrusion to main API of WIPI-HAL(Handset Adaptation Layer) and defines the prototype of mIDS(mobile IDS) API group that it can be added on the HAL. Moreover, we prove apply possibility through a WIPI emulator using java library.

• Journal of Korea Water Resources Association
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• v.53 no.10
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• pp.845-859
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• 2020

Climate change and recent heat waves have drawn public attention toward other environmental issues, such as water pollution in the form of algal blooms, chemical leaks, and oil spills. Water pollution by the leakage of chemicals may severely affect human health as well as contaminate the air, water, and soil and cause discoloration or death of crops that come in contact with these chemicals. Chemicals that may spill into water streams are often colorless and water-soluble, which makes it difficult to determine whether the water is polluted using the naked eye. When a chemical spill occurs, it is usually detected through a simple contact detection device by installing sensors at locations where leakage is likely to occur. The drawback with the approach using contact detection sensors is that it relies heavily on the skill of field workers. Moreover, these sensors are installed at a limited number of locations, so spill detection is not possible in areas where they are not installed. Recently hyperspectral images have been used to identify land cover and vegetation and to determine water quality by analyzing the inherent spectral characteristics of these materials. While hyperspectral sensors can potentially be used to detect chemical substances, there is currently a lack of research on the detection of chemicals in water streams using hyperspectral sensors. Therefore, this study utilized remote sensing techniques and the latest sensor technology to overcome the limitations of contact detection technology in detecting the leakage of hazardous chemical into aquatic systems. In this study, we aimed to determine whether 18 types of hazardous chemicals could be individually classified using hyperspectral image. To this end, we obtained hyperspectral images of each chemical to establish a spectral library. We expect that future studies will expand the spectral library database for hazardous chemicals and that verification of its application in water streams will be conducted so that it can be applied to real-time monitoring to facilitate rapid detection and response when a chemical spill has occurred.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.