• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.10
• /
• pp.1804-1809
• /
• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• 전자공학회논문지 IE
• /
• v.44 no.3
• /
• pp.12-22
• /
• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.10 s.340
• /
• pp.39-46
• /
• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• The Transactions of the Korean Institute of Power Electronics
• /
• v.10 no.2
• /
• pp.162-168
• /
• 2005

In this paper, a digital current mode control is designed for the power converter applications. The designed digital current mode controller is derived analytically from the continuous time small signal model of the power converters. Due to the small signal model based derivations of the control law, the designed control method can be applicable to boost, buck, and buck-boost converters. It is also proven that the controlled power converter employing the designed digital current mode controller is always stable regardless of an operating conditions. In order to show the usefulness of a designed controller, experiments are carried out using a 16bit DSP micro-processor, TMS320LF2406A.

• Journal of Practical Engineering Education
• /
• v.9 no.1
• /
• pp.41-48
• /
• 2017

In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.5
• /
• pp.11-11
• /
• 2001

본 논문에서는 카운터와 커패시터를 사용하여 시간 정보로부터 디지털 출력 값을 얻을 수 있는 새로운 시간-디지털 변환기를 제안하였다. 기존의 시간-디지털 변환회로의 경우 디지털 출력 값을 얻기 위해서는 입력 신호가 인가된 후 입력 시간보다 더 긴 공정시간이 필요하였다. 또한 입력 신호의 시간 간격에 무관하게 카운터의 클럭 주파수가 일정하여 변환된 디지털 값의 분해도는 항상 일정하였다. 그러나 본 논문에서 제안한 시간-디지털 변환 회로는 입력 신호가 인가됨과 동시에 지연시간 없이 디지털 출력 신호를 얻을 수 있으며, 또한 수동소자의 값을 변화시킴으로서 원하는 입력 시간 영역과 분해도를 쉽게 구현할 수 있다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.5
• /
• pp.193-197
• /
• 2017

In this paper, we present a low-power delta-sigma based digital frequency synthesizer with high frequency resolution for bio sensor networks. Biomedical radio-frequency (RF) transceivers require miniaturized forms with a long battery life and low power consumption. For the technology scaling, digital circuits have become preferable compared to analog circuits because of the aggressive cost, size, flexibility, and repeatability. Therefore, the digital circuits based on standard-cell library are used to reduce a power consumption. Additionally, a delta-sigma is used for making fractional frequency tuning range. From the simulation, we confirmed that proposed scheme has good performance in accordance with power and frequency resolution.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.9 no.1
• /
• pp.89-94
• /
• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• 전자공학회논문지 IE
• /
• v.47 no.2
• /
• pp.1-7
• /
• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.245-252
• /
• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.