• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.429-430
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• 2008

FFT(Fast Fourier Transform)는 멀티미디어 통신 및 디지털 신호처리 분야, 특히 무선통신이나 디지털 방송 등에서 쓰이는 OFDM(Orthogonal Frequency Division Multiplexing)에서 필수적인 역할을 하고 있다. 본 논문에서는 파이프라인 FFT 프로세서 설계의 다양한 알고리즘 및 하드웨어 구조에 대해 살펴보고 이를 한 눈에 파악할 수 있는 설계 가이드라인을 제시한다. 또한 분석 중 Radix-2 Single-path Delay Feedback의 복소곱셈기의 비효율적인 면을 찾고 새로운 R2SDF 구조를 제안한다.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2297-2298
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• 2008

최근, 공장 수용가들은 원격에서 인터넷 기반으로 전력정보를 감시, 상태를 진단, 제어함으로써 전기 사용의 안전성과 신뢰성 그리고 편이성을 제고할 수 있는 디지털 분전반을 필요로 하고 있다. 따라서 본 논문에서는 3상 수용가 시스템에서 요구되는 3상 디지털 분전반을 위한 전력관리 모듈이 설계된다. 제안되는 전력관리 모듈은 3상 4선식 전력공급방식으로 설계되며 3상 전력관리 디바이스가 전력신호 전처리기로 채택된다. 그리고 ARM 코아 기반의 32비트 프로세서가 제어모듈의 핵심 프로세서로 채택되며, 이더넷 컨버터를 통해 TCP/IP를 기반으로 하는 원격관리를 실현한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.673-682
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• 2004

The adaptive beam-forming is promising approach for noise reduction in hearing aids. This approach has come in the focus of interest only recently, because of the availability of new and powerful digital signal processors. The adaptation U using usually a Least Mean Squares algorithm, updates the weight vector. In this Paper, we propose a fast wavelet based adaptive algorithm using variable step size algorithm which varies adaptive constant by the change of signal environment. We compared the performance of the proposed algorithm with the known adaptive algorithm using computer simulation of multi channel adaptive bemformer in hearing aids. As the result the proposed algorithm is suitable for adaptive signal processing area using hearing aids and has advantages reducing computational complexity. And we show the beam-forming system using proposed algorithm converges stably in a sudden change of system environment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.131-137
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• 2005

Protective relays provide important features to electrical power systems for protecting against faults and consequent short circuits. This research presents a novel VLSI design of the digital protective relay, which overcomes today's uP/DSP-based relays. This design features good cancellation of DC/k-th harmonic components, noticeable not performance and flexible Protection behavior in the minimized core area The proposed design was successfully implemented by a FPGA(Field Programmable Gate Array) device and can concurrently process over 16KSPS at less $0.03[\%]$ error rate.

• Journal of Biomedical Engineering Research
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• v.16 no.4
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• pp.403-414
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• 1995

It is very difficult to quantize the ECG analysis because the decision criterion for ECG is different with each other depending on the medical specialists of the heart and there are measured detecting errors for each ECG measurement system. Therefore, we developed the real-time ECG identification system using digital fuzzy processor for STD-BUS, in order to reduce ambiguity generated in the process of ECG identification and to analyze the irregular ECG stastically to ECG's repetition interval. The variables such as AGE (months), width of QRS, average RRI, and RRI were used to classify the ECG, and were applied to ECG signal indentification system which is developed for the purpose of research. It was found that the automatic diagnosis of ECG signal was possible in the real time process which was impossible in general process of algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.18-20
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• 2000

디지털 음성통신을 위한 빠르고 쉬운 내장 프로세서(Embedded processor)가 요구되어짐에 따라 음성신호 압축 복원 알고리즘인 ADPCM과 LD-CELP의 구현에 가장 빈번히 사용되는 연산의 특성을 조사하였다. ARM6 processor core의 기본 구성요소들과 명령어집합을 기반으로 하여 음성부호화 알고리즘의 연산의 특성을 효율적으로 처리하기 위한 명령어와 구조를 추가한 범용 프로세서의 구조를 제안하고 VHDL로 기술하여 동작을 검증하였다. ARM6의 ALU logic에 leading zero count를 위한 회로를 추가하였고 opcode를 변경하였으며, LPC 계수 연산을 위해 제안된 MAC을 도입하여 효율적인 구현이 가능하도록 설계하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.61-64
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• 1994

디지털 신호를 처리하기 위해 특별히 제작된 ADSP-2105는 빠른 Fied-point 연산과 Harvard-architecture로 구조화됐기 때문에 빠른 수행연산을 할 수 가 있다. 본 논문은 이 DSP 프로세서를 이용해 음성신호의 실시간 FFT 분석에 관한 방법을 소개한다. 실시간 FFT 분석기로서의 DSP 보드는 크게 음성신호를 받는 입력부분과 FFT를 계산하는 FFT 부분으로 나뉘어지는데, 입력부분은 AD1849로 8KHz로 데이터를 샘플링해 받게 되었고, FFT 부분은 실제로 DSP가 FFT를 수행하는 부분으로 되어있다. 실시간 처리를 구현하기 위해 입력 부분은 두 개의 뱅크로 만들어 한 뱅크에서 음성신호를 받아들이는 동안에 다른 뱅크에서는 FFT를 계산하도록 되어있어서 DSP 보드는 항시 음성신호를 샘플링 할 수 있는 상태를 유지할 수 있다. 그리고 FFT 처리부는 빠른 처리로 음성신호를 샘츨링할 뱅크가 채워지기 전에 실행되게 프로그램되어 있어 실제적으로 모든 음성데이타를 FFT 하게 되어있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.153-156
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• 2009

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability ($0.22^{\circ}/hr$) and scale factor stability, extremely low angle random walk ($0.07^{\circ}/\sqrt{hr}$) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The CIC type of decimation block only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2291-2293
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• 2011

In this paper, the composes with digital position with a computer logical operation order with the signal processing method which is pliability and result of the logical operation which confronts in input signal from the outside input-output Channel leads and about the drive which the possibility to output at the outside is a research. This Decoder IC Multiplexer & De-multiplexer, position the function with from the digital signal circle where the imagination embodiments and BIT outputs of IC etc. are possible is possible in basic and usefully from the general industrial, could be used.

• Journal of the Korea Convergence Society
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• v.7 no.1
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• pp.9-15
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• 2016

In this paper, we describe the design of a high speed data acquisition system(DAS) with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the servo computer in real time. The system is designed for multi functions with universal asynchronous receiver and transmitter(UART), analog to digital converter(ADC), digital to analog converter(DAC), and general purpose input output(GPIO). those are well tested for various data acquisition and high speed motor control in real time.