• Journal of the Korea Academia-Industrial cooperation Society
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• 제7권6호
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• pp.1086-1091
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• 2006

In this paper an advanced PLL strategy suitable to UPS, compared with conventional PLL strategy using the positive sequence component extracted from source voltages, is suggested. Frequency limiter and anti-windup are added to conventional PI controller in suggested PLL strategy. Basic operational principle of suggested PLL is same as that of conventional PLL, but the difference between two strategies is that the suggested PLL can limit the change of frequency in constant range because of inclusion of frequency limiter. Compute. simulation was carried fer the DVR(dynamic voltage restorer) compensating voltage to examine the difference between conventional PLL strategy and the suggested PLL strategy limiting frequency. And the results clearly demonstrate the effectiveness of the suggested PLL strategy for UPS.

• The Transactions of the Korean Institute of Power Electronics
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• 제7권3호
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• pp.281-288
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• 2002

This paper has realized a control system of a vibrator using PM excited Transverse Flux Linear Motor(TFLM). Proposed vibrator can supply a vibration force up to 700[N] at rated current, wide operation range of vibration displacement and high frequency for a tested structure. Also, volume of a vibrator system can be decreased because of a high trust force rato(a thrust force per weight=N/Kg). A proposed vibrator instead of a hydraulic vibrator can improve efficiency and have may advantages of maintenance and management. A desired value command is a vibration frequency and displacement in a controller for a vibrator system and a controlled values we a instant position and velocity of a mover Output value of the controller is phase current controlled by PWM converter. In this research, Dynamic simulation has been executed for analysis of a control algorithm and dvnauuc characteristics and is compared with experimental result.

• Journal of the Korean Society of Propulsion Engineers
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• 제18권2호
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• pp.27-34
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• 2014

Buzz margin scheduling and control technique which are suitable to regulate stable and high pressure air in wide range of Mach number are suggested for fixed geometry of a supersonic intake. From the analysis of preceding study, most effective control variable is induced and scheduling law is newly suggested in a real application point of view. The appropriateness of the control law in wide range of Mach number is addressed by numerical simulation of controlled propulsion system. Also, the simulation for stabilization and tracking performances of the controller are studied to investigate the phenomena under flight maneuver and disturbances.

• The Transactions of the Korean Institute of Electrical Engineers A
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• 제49권1호
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• pp.6-12
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• 2000

This paper presents various processes of dynamic voltage collapse which is initiated by various power system disturbances, and the impacts of dynamic voltage controllers. According to the analysis results, the composition of induction motors with short time constants affects the voltage collapse strongly. Also, it is proved that the addition of fast acting reactive compensation devices, such as SVC, at high reactive loss sensitivity($$\delta$$Q$$_luss/\delta$$P$$_L$$) buses could be one of the best countermeasure to escape the voltage collapse.

• Proceedings of the KIEE Conference
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• 대한전기학회 1992년도 하계학술대회 논문집 A
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• pp.354-358
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• 1992

본 연구에서는 n-차 비선형 로보트 매니퓰레이터에서 링크의 동특성에 액류웨이터의 동특성을 포함시킨 복합모델(Combined Model)의 알고리즘을 제안하였다. 여기서 이 복합 모델의 알고리즘은 고속운전 및 빈번한 부하의 변동시에 중요한 역할을 하는 액류웨이터 모터의 동특성 방정식과 매니퓰레이터 링크의 운동을 묘사하는 동특성 방정식을 포함시킨 알고리즘을 의미한다. 또한 제안된 모델은 선영궤환 및 감결합 변환(Feedback Linearizing and Decoupling Transformation : FLDT)법을 이용하여 선형시스템으로 변환시켰다. 따라서 본 연구에서는 고속운전 및 빈번한 부하의 변동에도 액류웨이터 모터의 전압과 전류를 조절함으로써 효과적으로 제어할 수 있게 하는 매니퓰레이터 모델 알고리즘을 개발하는데 그 목적이 있다.

• Proceedings of the KIPE Conference
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.36-40
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• 2003

On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. The control delay in digital controllers increases the dimension of the system transfer function one degree higher which makes the control system more complicate and more unstable. Based on the power stage analysis, a novel controller for the compensation voltages in DVRs is proposed by a feedforward control scheme. Proposed controller works well with the time delay in the digital control system. This paper also proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs in digital controllers. Proposed theory is verified by an experimental DVR system with a typical digital controller.

• Proceedings of the KIEE Conference
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.886-890
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• 1997

This paper presents shows various process of dynamic voltage collapses which were initiated by power system disturbances, and the impacts of dynamic voltage controllers. According to the analysis results, the composition of induction motors with short time constant strongly affect the voltage collapse. To escape the voltage collapse, adding fast acting reactive compensation device, such as SVC, at high reactive loss sensitivity(${\partia}Qloss/{\partia}PL$) point could be one of a good countermeasure.

• Proceedings of the KIEE Conference
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.1097-1099
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• 1997

The implementation of Static Var Compensator(SVC) provides opportunites to maintain voltage profile and improve voltage stability in large scale power system. Under Load Tap Changing(ULTC) transformer has been used to control the voltage. It is necessary that Coordinated control of SVC and ULTC for the better performance. This paper shows that the characteristic of Voltage control using SVC or ULTC and the condition of the coordinated control considering dynamic voltage stability.

• Journal of Korea Multimedia Society
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• 제8권8호
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• pp.1042-1050
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• 2005

This paper proposed a novel low-power video decoding scheme for mobile multimedia communication. In general, there are quite a large number of non-coded blocks in the encoded bitstream where all quantized DCT coefficients are truncated into zero. When the number of the non-coded blocks are known at the start of frame decoding, the amount of computation reduction can be precisely estimated for frame decoding. When the computation reduces, the operation speed and the corresponding supply voltage of VLSI circuits in the decoder also reduce, thus thus power consumption also reduces. In the proposed scheme, the number of the non-coded blocks is stored in the frame header of the encoded bitstream, and the decoder efficiently reduces the power consumption exploiting this information. Simulation results show that the proposed scheme reduces the power consumption to about 1/20.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제47권7호
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• pp.52-60
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• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.