• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2208-2220
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• 1997

This paper presents a distributed multimedia synchronization algorithm that supports both intramedia and intermedia synchronizations. The intramedia synchronization is achieved by media scaling techniques, and the intermedia synchronization is achieved by variable service rates. We compute the check period between master media's and slave media's relative time stamps for intermedia synchronization. We also evaluate our algorithm through simulations. Simulation results show that our algorithm performs well in both intramedia and intermedia synchronizations.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
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• 2003.09a
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• pp.11-11
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• 2003

오늘날 단일 슈퍼컴퓨터로는 처리가 불가능한 거대한 문제들의 해법이 시도되고 있는데, 이들은 지리적으로 분산된 슈퍼컴퓨터, 데이터베이스, 과학장비 및 디스플레이 장치 등을 초고속 통신망으로 연결한 GRID 환경에서 효과적으로 실행시킬 수 있다. GRID는 1990년대 중반 과학 및 공학용 분산 컴퓨팅의 연구 과정에서 등장한 것으로, 점차 응용분야가 넓어지고 있다. 그러나 GRID 같은 분산 환경은 기존의 단일 병렬 시스템과는 많은 점에서 다르며 이전의 기술들을 그대로 적용하기에는 무리가 있다. 기존 병렬 시스템에서는 주로 동기 알고리즘(synchronous algorithm)이 사용되는데, 직렬 연산과 같은 결과를 얻기 위해 동기화(synchronization)가 필요하며, 부하 균형이 필수적이다. 그러나 부하 균형은 이질 클러스터(heterogeneous cluster)처럼 프로세서들의 성능이 서로 다르거나, 지리적으로 분산된 계산자원을 사용하는 GRID 환경에서는 이기종의 문제뿐 아니라 네트워크를 통한 메시지의 전송 지연 등으로 유휴시간이 길어질 수밖에 없다. 이처럼 동기화의 필요성에 의한 연산의 지연을 해결하는 하나의 방안으로 비동기 반복법(asynchronous iteration)이 나왔으며, 지금도 활발히 연구되고 있다. 이는 알고리즘의 동기점을 가능한 한 제거함으로써 빠른 프로세서의 유휴 시간을 줄이는 것이 목적이다. 즉 비동기 알고리즘에서는, 각 프로세서는 다른 프로세서로부터 갱신된 데이터가 올 때까지 기다리지 않고 계속 다음 작업을 수행해 나간다. 따라서 동시에 갱신된 데이터를 교환한 후 다음 단계로 진행하는 동기 알고리즘에 비해, 미처 갱신되지 않은 데이터를 사용하는 경우가 많으므로 전체적으로는 연산량 대비의 수렴 속도는 느릴 수 있다 그러나 각 프로세서는 거의 유휴 시간이 없이 연산을 수행하므로 wall clock time은 동기 알고리즘보다 적게 걸리며, 때로는 50%까지 빠른 결과도 보고되고 있다 그러나 현재까지의 연구는 모두 어떤 수렴조건을 만족하는 선형 시스템의 해법에 국한되어 있으며 비교적 구현하기 쉬운 공유 메모리 시스템에서의 연구만 보고되어 있다. 본 연구에서는 행렬의 주요 고유쌍을 구하는 데 있어 비동기 반복법의 적용 가능성을 타진하기 위해 우선 이론적으로 단순한 멱승법을 사용하여 실험하였고 그 결과 순수한 비동기 반복법은 수렴하기 어렵다는 결론을 얻었다 그리하여 동기 알고리즘에 비동기적 요소를 추가한 혼합 병렬 알고리즘을 제안하고, MPI(Message Passing Interface)를 사용하여 수원대학교의 Hydra cluster에서 구현하였다. 그 결과 특정 노드의 성능이 다른 것에 비해 현저하게 떨어질 때 전체적인 알고리즘의 수렴 속도가 떨어지는 것을 상당히 완화할 수 있음이 밝혀졌다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1033-1036
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• 1998

본 논문은 FLEX 디코더에서 필요한 심볼 클럭을 생성하기 위한 심볼 동기 알고리즘을 제안하고, 제안한 알고리즘을 기본으로 한 심볼을 동기회로의 설계에 관한 것이다. 제안한 알고리즘은 조-만 게이트 동기 (ELGS:Early-Late Gate Synchronization)기법을 이용하고 있다. VHDL(VHSIC Hardware Description Language)로 설계된 심볼 동기회로는 Synopsys 툴을 이용하여 기능레벨의 시뮬레이션을 수행하였고, Altera MAX+plus II를 이용하여 타이밍 분석을 수행하였다. 실험 결과로부터 Source unit와 FLEX 디스코더와의 시스템 동기가 정확히 이루어짐을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.874-881
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• 2008

This paper presents an automatic frequency control algorithm for RTLS DS-SS modem based on the standard of ISO/IEC 24730-2. The presented automatic frequency control algorithm consists of frequency acquisition mode and frequency tracking mode, and the frequency acquisition mode is divided into the angle estimation step for frequency offset estimation and the verification step for removing the angle ambiguity. In the angle estimation step, three different sub-bit angles are estimated according to the timing intervals, then the estimates are used to re move the angle ambiguity in the verification step. The theoretical analysis and the simulation results of the proposed frequency control algorithm are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.159-166
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• 2008

In this paper, we proposed an algorithm to solve the problem that can't maintain hop synchronization using only early-late gate tracking loop due to the drift of geo-stationary satellite in frequency hopping satellite communication system. When the signal is transferred to downlink through DRT(Dehop-Rebop Transponder), the problem with synchronization loss is occurred periodically when using only early-late gate tracking loop, because of energy loss in each side portion of hop due to orbital variation of the satellite. To solve this problem, we have developed Anti-Shrink synchronization tracking algorithm which uses the prediction value of transmission timing and the structure of inner-outer gate instead of early-late gate with the ranging information. Through simulations, we showed that the performance of the Anti-Shrink algorithm is better than that of simple inner-outer energy ratio algorithm and similar to that of conventional early-late tracking loop algorithm with ranging information. No synchronization failure in the proposed algorithm was occurred because of less energy loss and robustness without the ranging information.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.67-74
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• 2004

Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.842-854
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• 1997

In this paper, the improved Dual Leaky-Bucket(DLB) algorithm is proposed to reduce the synchronous cell loss rate. The conventional DLB algorithm does not support synchronous cells, but the proposed algorithm gives higher priority to synchronous cells. To reduce synchronous cell loss rate, the synchronous cell detector is used in the proposed algorithm. Synchronous cell detector detects synchronous cells, and passes them cells to the 2nd Leaky-Bucket. So it is similar to give higher priority to synchronous cells. In this paper, the proposed algorithm used audio/videl traffic modeled by On/Off and Two-state MMPP, and simulated by SLAM II package. As simulation results, the proposed algorithm gets lower synchronous cell loss rate than the conventional DLB algorithms. The improved DLB algorithm for multimedia synchronization can be extended to any other cells which require higher priority.

• Journal of Advanced Navigation Technology
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• v.5 no.1
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• pp.45-53
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• 2001

We present the frame synchronization scheme using the FFT window position restoration algorithm appropriate for wireless OFDM systems under multipath fading environment. From the restoration of the synchronization parameters of previous several frames, the algorithm can extract the synchronization parameters for the next frames. To analyze the performance of the proposed algorithm, we compare the probability of synchronization failure under time and frequency domains, respectively. From the simulation results, one can see that the algorithm in the time domain shows better performance than in the frequency one, for the $E_b/N_o$ of 6.0dB or more.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.3
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• pp.545-553
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• 2017

This paper investigates a synchronization algorithm for a distributed network which does not have a centralized infrastructure. In order to operate a distributed network, synchronization across distributed terminals should be acquired in advance, and hence, a plenty of distributed synchronization algorithms have been studied extensively in the past. However, most of the previous studies focus on the synchronization only in fault-free networks. Thus, if there are some malfunctioning terminals in the network, the synchronization can not be guaranteed with conventional distributed synchronization methods. In this paper, we propose a reliability-based adaptive consensus algorithm which can effectively acquire the synchronization across distributed terminals and confirm performance of the proposed algorithm by conducting numerical simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.