• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1727-1736
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• 2006

In a fuzzy control system to vocess fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent Pan and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose novel integer fuzzy operation method without mulitplications and divisions by only integer addition to convert real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$ without [0, 1] real operations. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.668-675
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• 2002

This paper proposes pre-distorter combined LUT with 2ιpartition interpolation method to reduce nonlinear distortion which was caused by high PAPR and to update LUT quickly. Pre-distorted gain and phase can be found by using LUT which consisted of AM/AM and AM/PM value, and OFDM signal amplitude. The proposed 2ιpartition interpolation can accurately find predistorted gain and phase using bit shift and add component instead of increasing size of LUT which requires increasing the amount of computation. The performance of the proposed method was measured by the difference between HPA input and output characteristics by the LUT size, constellation, SER performance by the HPA, and LUT update error by the HPA characteristic changes. As a result, it is shown that when the size of the LUT is 32 and 64 for 16-QAM and 64-QAM, nonlinear distortion nearly didn't occurred.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• Journal of Advanced Marine Engineering and Technology
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• v.19 no.1
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• pp.60-70
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• 1995

In the field of marine transportation the energy saving is one of the most important factors for profit. In order to reduce the fuel oil consumption the ship's propulsion efficiency must be increased as much as possible. The propulsion efficiency depends upon a combination of an engine and a propeller. The propeller has better efficiency as lower rotational speed. This situation led the engine manufacturers to design the engine that has lower speed, longer stroke and a small number of cylinders. Consequently the variation of rotational torque became larger than before because of the longer delay-time in the fuel oil injection process and an increased output per cylinder. As this new trends the conventional mechanical-hydrualic governors for engine speed control have been replaced by digital speed controllers which adopted the PID control or the optimal control algorithm. But these control algorithms have not enough robustness to suppress the variation of the delay-time and the parameter pertubation. In this paper we consider the delay-time and the perturbation of engine parameters as the modeling uncetainties. Next we design the controller which has zero offset in steady state engine speed, based on the two-degree-of-freedom control theory and $\mu$-synthesis. Thd validity of the controller is investigated through the response simulation. We use a personal computer and an analog computer as the digital controller and the engine (plant) part respectively. And, we certify that the designed controller maintains its performance even though the engine parameters may vary.

• Korean Journal of Logic
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• v.22 no.3
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• pp.417-446
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• 2019

The operation theory of the Wittgenstein's Tractatus Logico-Philosophicus is the essential basis of the philosophy of mathematics of the Tractatus. Wittgenstein presents the definition of cardinal numbers on the basis of operation theory, and suggests the proof of "$2{\times}2=4$" by using the theory of operations in 6.241. Therefore, in order to explicate correctly the philosophy of mathematics, it is required to understand rigorously the theory of operations in the Tractatus. Accordingly in this paper, I will endeavor to explicate operation theory of the Tractatus as a preliminary study for explicating the philosophy of mathematics of the Tractatus. In this process, we can ascertain Frascolla's important contributions and fallacies in his reconstruction of 6.241. In particular, we can understand the background that in 6.241 Wittgenstein made mistakes and that there he dealt with the addition operation of the theory of operations, and on the basis of this, we can reconstruct correctly 6.241.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.