• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1217-1224
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• 2003

In this paper, we propose an edge side-lobe suppressor (ESS) for the uplink of OFDMA systems, which mitigates the interference introduced by different frequency offsets between a desired user and the other users. We evaluate the proposed ESS scheme by measuring average signal to interference ratio (SIR) and average bit error rate (BER). The simulation results confirm that the proposed ESS scheme improves system performance by approximately 5∼10 dB SIR as compared to conventional OFDMA systems. Because the additional operations for the proposed scheme can be performed by a real-valued look-up table, the implementation of the ESS hardly requires increasing transmitter and receiver complexity.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.1
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• pp.37-42
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• 2009

The digital filter is essential element in digital signal processing area. It needs a high computational burden caused by multiplying and adding. The multiplier in digital filter is a dominant element, which occupies an wide area at the field of VLSI design, needs high power-consuming and also decides critical path that affects to filter performance. In this paper we proposed the simultaneous transform method which is represented 2's complementary representation to CSD and MSD representation to solve a complexity problem and to improve a computational speed. The performance of proposed method was implemented in VHDL and applied to an digital filters, was evaluated the decreasing of critical path delay.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.42-48
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• 2014

In this paper, we propose a new small swing domino logic that reduces the swing amplitude by using twist-connected PMOS and NMOS transistors. The output swing range of the proposed circuit is adjusted by the size of the twist-connected transistors and the load capacitance. The designed RCA with the proposed circuit technique shows reduction of the power consumption by 37% and PDP performance by 43% compared with the domino CMOS logic.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.345-348
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• 1999

본 논문에서는 내장형 응용에 적합한 RISC 마이크로프로세서와 DSP 프로세서의 기능을 유기적으로 결합한 구조를 연구하고 이를 설계한다. 프로그램의 크기를 줄이기 위해 RISC 명령어는 16비트 명령어 집합을 설계하고 분기 명령어로 인한 손실을 줄이기 위해 한 개의 지연 슬롯을 갖고 있다. DSP 명령어는 32비트 길이를 갖고 한 명령어로 곱셈, 덧셈(뺄셈), 두 가지 데이터 이동을 할 수 있어서 한 사이클에 최대 네 가지 동작을 할 수 있다 파이프라인 단계는 IF, ID, EX, MA, WB/DSP의 다섯 단계로 구성된다. DSP 기능을 지원하기 위해 내부 루프 버퍼를 갖고 정수 실행부에서는 주소 발생을 위한 전용 하드웨어와 DSP 유닛에서는 곱셈 및 누적 기능을 지원하기 위한 17 × 17 비트 곱셈기가 내장된다. 제안된 구조의 설계는 Verilog-HDL을 이용하여 top-down 설계 방식으로 설계되었고 각 기능 검증을 마친 후 3.3V, 0.6㎛ CMOS triple metal single poly 공정을 이용하여 합성하고 레이아웃 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2714-2726
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• 1997

In this paper, adaptive symbol changes-based medical image compression method is presented. First, the differenctial image domain is obtained using the differentiation rules or obaptive predictors applied to original mdeical image. Also, the algorithm determines the context associated with the differential image from the domain. Then prediction symbols which are thought tobe the most probable differential image values are maintained at a high value through the adaptive symbol changes procedure based on estimates of the symbols with polarity coincidence between the differential image values to be coded under to context and differential image values in the model template. At the coding step, the differential image values are encoded as "predicted" or "non-predicted" by the binary adaptive arithmetic encoder, where a binary decision tree is employed. The simlation results indicate that the prediction hit ratios of differential image values using the proposed algorithm improve the coding gain by 25% and 23% than arithmetic coder with ISO JPEG lossless predictor and arithmetic coder with differentiation rules or adaptive predictors, respectively. It can be used in compression part of medical PACS because the proposed method allows the encoder be directly applied to the full bit-planes medical image without a decomposition of the full bit-plane into a series of binary bit-planes as well as lower complexity of encoder through using an additions when sub-dividing recursively unit intervals.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.74-81
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.781-783
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• 2000

1bit full adder have 3 input (including carry_in) and 2 outputs(Sum and Carry_out). Because of 1 bit full adder's propagation delay. We usually use 4-bit binary full adder with fast carry, 74LS283. The 74LS283 is positive logic circuit chip. But the logic function of binary adder is symmetrical, so it can be possible to use it not only positive logic but also the negative logic. This thesis use symmetrical property. such as $C_{i+1}(\bar{a_i}\bar{b_i}\bar{c_i})=C_{i+1}{\bar}(a_i,\;b_i,\;c_i)$ and $S_i(\bar{a_i}\bar{b_i}\bar{c_i})=\bar{S_i}(a_i,\;b_i,\;c_i)$. And prove this property with logic operation. Using these property, the 74LS283 adder is possile as the negation logic circuit. It's very useful to use the chip in negative logic. because many system chip is negative logic circuit. for example when we have negative logic chip with 74LS283. we don't need any not gate for 74LS283 input, and just use output of adder(74LS283) as the negation of original output.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.52-62
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• 2006

In a fuzzy control system to process fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent part and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose an integer line mapping algorithm using only integer addition to convert [0,1] real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$. This paper also shows a novel defuzzification algorithm without multiplications. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.