• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.111-120
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• 2005

A cost effective three-dimensional color gamut mapping architecture is described. The conventional three-dimensional reduced resolution look-up table is considered and the concept of three-dimensional reduced resolution difference look-up table is introduced for cost effective and real-time color gamut mapping. The overall architecture uses one-dimensional memory decomposition of three-dimensional gamut mapping look-up table, three-dimensional interpolation and simple addition operation for generating the final gamut mapped colors. The required computational cost is greatly reduced by look-up table resolution adjustment and further reduced by the gamut mapping rule modification. The proposed architecture greatly reduces the required memory size and hardware complexity compared to the conventional method and it is suitable for real-time applications. The proposed hardware is suitable for FPGA and ASIC implementation and could be applied to the real-time display quality enhancement purposes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.973-980
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• 2006

In most of the studies on locally optimum detection assumes independent observations. The use of an independent observation model may cause a considerable performance degradation in detection applications of modern high data rate communication systems exhibiting dependence among interference components. In this paper, we address the detection of weak known signals in multiplicative and first order Markov additive noises. In Part 1, the test statistics of the locally optimum detectors are investigated in detail. In Part 2, the asymptotic and finite sample-size performance of several detectors are obtained and compared, confirming that the dependence among interference components need to be taken into account to maintain performance appropriately.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.252-265
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• 2000

In this thesis, the analysis of data processing method and the amount of computation in the whole geometry processing is conducted step by step. Floating-point ALU design is based on the characteristics of geometry processing operation. The performance of the devised ALU fitting with the geometry processing operation is analyzed by simulation after the description of the proposed ALU and geometry processor. The ALU designed in the paper can perform three types of floating-point operation simultaneously-addition/subtraction, multiplication, division. As a result, the 23.5% of improvement is achieved by that floating-point ALU for the whole geometry processing and in the floating-point division and square root operation, there is another 23% of performance gain with adding area-performance efficient SRT divisor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.55-64
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• 2005

In this paper, we designed floating point units to accelate real-time 3D Graphics for Geometry processing. Designed floating point units support IEEE-754 single precision format and we confirmed 100 MHz performance of floating point add/mul unit, 120 MHz performance of floating point NR inverse division unit, 200 MHz performance of floating point power unit, 120 MHz performance of floating point inverse square root unit at Xilinx-vertex2. Also, using floating point units, designed Geometry processor and confirmed 3D Graphics data processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8A
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• pp.1348-1357
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• 2001

본 논문에서는 DAB 시스템에서 사용하는 FEC(Forward Error Correction) 블록을 하드웨어 크기를 고려하여 효율적인 구조를 갖도록 설계하였다. DAB 시스템의 FEC 블록은 크게 스크램블러(에너지분산), 리드-솔로몬 코더, 길쌈 인터리버로 구성된다. RS 디코더 블록 중 키 방정식을 계산해 내는 블록과 길쌈 인터리버가 차지하는 하드웨어 비중은 굉장히 크다. 본 논문에서는 스크램블러 부분에서 데이터의 시작을 알려주는 신호의 효율적인 검출기법을 제안하고, 리드-솔로몬 디코더 블록의 수정 유클리드 알고리즘을 효율적인 하드웨어로 구현하기 위한 새로운 구조와 길쌈 인터리버에서 최적의 메모리 구조를 효과적인 구조를 제안한다. 제안한 구조에서는 단지 8개의 GF 곱셈기와 4개의 덧셈기만을 가지고 RS 디코더의 수정 유클리드 알고리즘을 구현하였으며, 2 RAM(128)과 4 RAM(256)을 가지고 컨벌루셔널 인터리버를 구현하였다. 제안한 구조로 설계했을 경우 디코더 블록이 Altera-FPGA 칩(FLEX10K)에 모두 들어갈 수 있었다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1089-1092
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• 1998

Conventional floating-point adders have one data-path that is used for all operations. This paper describes a floatingpoint adder eeveloped for low power consumption, which has three data-paths one of which is selected according to the exponent difference. The first is applied to the case that the absolute exponent difference (AED) of two operands is less than 1, and the second is for 1

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.255-258
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• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.121-125
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• 2014

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.47-55
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• 1997

In general, processing flow of the conventional floating-point multiplication consists of either multiplication, addition, normalization, and rounding stage of the conventional floating-point multiplier requries a high speed adder for increment, increasing the overall execution time and occuping a large amount of chip area. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by using the carry select addder used in the addition stage and optimizing the operational flow based on the charcteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this paper. The proposed floating point multiplier does not require and additional execution time nor any high spped adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this suggested approach.

• Korean Journal of Computational Design and Engineering
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• v.7 no.4
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• pp.269-279
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• 2002

Geometric shape morphing is an interesting geometric operation that interpolates two geometric shapes to generate in-betweens. It is well known that Minkowski operations can be used to test and build collision-free motion paths and to modify shapes in digital image processing. In this paper, we present a new geometric modeling technique to control the morphing on geometric shapes based on Minkowski sum. The basic idea develops from the linear interpolation on two geometric shapes where the traditional algebraic sum is replaced by Minkowski sum. We extend this scheme into a Bezier-like control structure with multiple control shapes, which enables the interactive control over the intermediate shapes during the morphing sequence as in the traditional CAGD curve/surface editing. Moreover, we apply the theory of blossoming to our control structure, whereby our control structure becomes even more flexible and general. In this paper, we present mathematical models of control structure, their properties, and computational issues with examples.