• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.614-616
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• 2003

기존의 비디오 코딩에서는 연속된 프레임의 시간적인 상관성을 제거하기 위한 방법으로 이전 프레임의 정보를 이용하여 현재 프레임을 예측하는 움직임 예측기법을 많이 사용하고 있다. 정지 화상에 비해서 대용량의 특성을 지니는 비디오 데이터는 이런 움직임 예측을 통해서 대부분의 압축이 일어나게 된다. 하지만 움직임 예측기법은 않은 계산과정을 요구하므로, 전체적인 부호기 복잡도를 높이는 단점을 지닌다. 반면 30-WT는 움직임 예측을 하지 않으므로, 부호기의 복잡도를 줄일 수 있다. 하지만. 기존의 30-WT기법들은 부호화를 위한 메모리 요구사항과 복호를 위한 수신측의 지연시간이 가장 큰 단점으로 지적되었다. 따라서, 본 논문에서는 메모리 요구사항과 수신측의 지연시간을 최소로 할 수 있는 효율적이고, 확장가능한 3D-WT 기법을 소개한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.697-699
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• 2015

본 논문에서는 하둡의 인메모리 기반 ACL(access control list)을 RDBMS 기반으로 관리하도록 기존 하둡을 재설계하였다. 기존 하둡은 ACL을 인메모리에서 관리하기 때문에 대용량 ACL 정보를 관리함에 있어 메모리 오버헤드, ACL 정보 관리의 비효율성 등 몇 가지 문제가 발생할 수 있다. 본 논문에서는 ACL 관리에 RDBMS를 사용함으로써 메모리 크기에 종속되지 않으며, 외부 응용 프로그램에서도 쉽고 일관성있게 ACL 정보를 관리할 수 있다. 이 같은 결과에 따라, 본 논문은 빅데이터를 하둡에서 안정하게 관리할 수 있는 우수한 연구 설계 결과라 생각된다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.169-172
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• 2010

최근 플래시 메모리뿐만 아니라 SSD 를 활용한 데이터베이스의 사용이 점차 늘어나고 있다. 대용량의 데이터를 처리하는 데이터베이스에서는 삽입, 삭제, 검색을 빠르게 하기 위해 다양한 색인기법을 사용하는데 그 중 B-트리 구조가 대표적인 기법이다. B-트리는 삽입, 삭제, 검색을 할 때 더 나은 성능을 갖도록 도와주지만 그 구조를 유지하기 위한 비용이 많이 들어간다는 단점이 있다. 그 중 하나로 삽입 시 키가 삽입된 단말노드뿐만 아니라 그 부모노드까지 수정이 되어 한 번의 삽입에 여러 노드가 여러 페이지에 씌어져서 삽입시간이 길어지는 단점이 있다. 본 논문에서는 이러한 단점을 개선하기 위하여 SSD 에서 데이터베이스를 사용할 때 SSD 의 병렬 접근(parallel access) 방식을 사용해서 수정된 단말노드부터 루트노드까지의 경로에 있는 모든 노드들을 연속한 논리 주소 공간에 쓰는 방식을 적용하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• Smart Media Journal
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• v.3 no.1
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• pp.33-38
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• 2014

Even though the performance of microprocessor is improved continuously, the performance improvement of computing system becomes hard to increase, in order to some drawbacks including increased power consumption. To solve the problem, general-purpose computing on graphics processing units(GPGPUs), which execute general-purpose applications by using specialized parallel-processing device representing graphics processing units(GPUs), have been focused. However, the characteristics of applications related with graphics is substantially different from the characteristics of general-purpose applications. Therefore, GPUs cannot exploit the outstanding computational resources sufficiently due to various constraints, when they execute general-purpose applications. When designing GPUs for GPGPU, memory system is important to effectively exploit the GPUs since typically general-purpose applications requires more memory accesses than graphics applications. Especially, external memory access requiring long latency impose a big overhead on the performance of GPUs. Therefore, the GPU performance must be improved if hierarchical memory architecture which can reduce the number of external memory access is applied. For this reason, we will investigate the analysis of GPU performance according to hierarchical cache architectures in executing various benchmarks.

• Bulletin of the Korean Space Science Society
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• 2007.10a
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• pp.90.1-90.1
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.26-33
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• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.29 no.1
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• pp.39-46
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• 2011

The present study introduces a comparison between 3D R-tree and octree which are noticeable candidates to index large point clouds gathered from a 3D terrestrial laser scanner. A query method, which is to find neighboring points within given distances, was devised for the comparison, and time lapses for the query along with memory usages were checked. From tests conducted on point clouds scanned from a building and a stone pagoda, it was shown that octree has the advantage of fast generation and query while 3D R-tree is more memory-efficient. Both index and leaf capacity were revealed to be ruling factors to get the best performance of 3D R-tree, while the number of level was of oetree.

• Journal of KIISE:Databases
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• v.37 no.5
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• pp.275-284
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• 2010

GPUs are stream processors based on multi-cores, which can process large data with a high speed and a large memory bandwidth. Furthermore, GPUs are less expensive than multi-core CPUs. Recently, usage of GPUs in general purpose computing has been wide spread. The CUDA architecture from Nvidia is one of efforts to help developers use GPUs in their application domains. In this paper, we propose techniques to parallelize a skyline algorithm which uses a simple nested loop structure. In order to employ the CUDA programming model, we apply our optimization techniques to make our skyline algorithm fit into the performance restrictions of the CUDA architecture. According to our experimental results, we improve the original skyline algorithm by 80% with our optimization techniques.