• Journal of IKEEE
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• v.22 no.4
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• pp.1168-1174
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• 2018

For the initial state of NAND flash memories, error-free and single-error cases are dominant due to a good channel environment on memory cells. It is important to deal with such cases, which affects the overall system performance. However, the conventional schemes for polar codes equally decode the codes even for the error-free and single-error cases since they cannot classify and decode separately. In this paper, a new pre-processing scheme for polar codes is proposed so as to improve the overall decoding latency by decoding the frequent error-free and single-error cases. Before the ordinary decoding process, the proposed scheme first decodes the frequent error-free and single-error cases. According to the experimental results, the proposed pre-processing scheme decreases the average decoding latency by 64% compared to the conventional scheme for (1024, 512) polar codes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.327-334
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• 2016

In this paper, we propose a hardware architecture of transform and quantization for high-perfornamce HEVC(High Efficiency VIdeo Coding) encoder. HEVC transform decides the transform mode by comparing RDCost to search for the best mode of them. But, RDCost is computed using the bit-rate and distortion which is computed by transform, quantization, de-quantization, and inverse transform. Due to the many calculations and encoding time, it is hard to process high resolution and high definition image in real-time. This paper proposes the method of transform mode decision by comparing sum of coefficient after transform only. We use BD-PSNR and BD-Bitrate which is performance indicator. Based on the experimental result, We confirmed that the decision of transform mode can process images with no significant change in the image quality. We reduced hardware area by assigning different values at the same output according to the transform mode and overlapping coefficient multiplied as much as possible. Also, we raise performance by implementing sequential pipeline operation. In view of the larger process that we used compared with the process of reference paper, Our design has reduced by half the hardware area and has increased performance 2.3 times.

• Journal of Broadcast Engineering
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• v.12 no.6
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• pp.596-610
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• 2007

In order to reduce the complexity of SVC encoding, we introduce a fast mode decision method in the enhancement layers of spatial scalability by selectively performing the inter-layer residual prediction of SVC. The Inter-layer residual prediction coding in Scalable Video Coding has a large advantage of enhancing the coding efficiency since it utilizes the correlation between two residuals from a lower spatial layer and its next higher spatial layer. However, this entails the dramatical increase in the complexity of SVC encoders. The proposed method is to analyze the characteristics of integer transform coefficients for the subtracted signal for two residuals from lower and upper spatial layers. Then it selectively performs the inter-layer residual prediction coding and rate-distortion optimizations in the upper spatial enhancement layer if the SAD values of residuals exceed adaptive threshold values. Therefore, by classifying the residuals according to the properties of integer-transform coefficients only with SAD of residuals between two layers, the SVC encoder can perform the inter-layer residual coding selectively, thus significantly reducing the total required encoding time. The proposed method results in reduction of the total encoding time with 51.5% in average while maintaining the RD performance with negligible amounts of quality degradation.

• Journal of Broadcast Engineering
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• v.20 no.3
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• pp.388-397
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• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.591-597
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• 2008

In this paper, we present a improved rate distortion optimization (RDO) for H.264 intra coding. By using new mode decision criteria pass for $I4{\times}4$ in company with the original RDO, the proposed method can achieve the better coding efficiency comparing with the original RDO. Our experimental results show that the proposed algorithm can archive about $0.64{\sim}1.6578%$ bit rate decrease at the same PSNR and $0.049{\sim}0.101dB$ PSNR increase at the same bit rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1728-1730
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• 2015

In this letter, a parity check based iterative IC scheme is proposed for LDPC coded MIMO systems. After the decoding procedures in each iteration of the proposed scheme, each decoded codeword is utilized for the IC procedures only when the ratio of the check nodes satisfying the parity check equations to the total number of check nodes is not smaller than the pre-defined threshold value. Simulation results verify that the proposed scheme can achieve an improved BLER at the high SNR region compared to the conventional iterative IC scheme.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.1
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• pp.31-39
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• 2014

The performance of fuel cell/gas turbine hybrid systems is highly affected by system configuration. In this study, the performance of a hybrid system combining a molten carbonate fuel cell (MCFC) and an indirectly fired gas turbine was predicted. Firstly, general performance trends of the hybrid system depending on major design parameters were examined. Then, the most feasible design options with the least impact on the MCFC stack design conditions were drawn. The economic advantage of the hybrid system over the basic MCFC only system was evaluated.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.320-321
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• 2011

본 논문은 디지털 케이블전송망인 HFC(Hybrid Fiber and Coaxial)망 기반하에서 6MHz 다수의 방송채널결합 기술을 이용하여, 대용량 3D 및 8K-UHD 콘텐츠 전송을 위한 방송망 채널결합형 200Mbps 급 1024-QAM 송수신시스템 개발에 대하여 기술한다. H.264 비디오 부호화기를 사용하여 8K-UHDTV 및 3D/UHD 융합형 서비스를 시청자에게 제공하기 위해서는 약 120~160Mbps 의 대용량 데이터 전송률이 확보되어야 한다. 이와같이 대용량 3D/8K-UHDTV 콘텐츠를 전송하기 위해서는 상대적으로 채널환경이 우수한 HFC 디지털 케이블망을 이용한 대용량 실감미디어 콘텐츠 전송기법에 대한 연구가 주목 받고 있다. 본 논문에서는 FPGA 를 이용하여 HFC 망 기반에서 기존 OpenCalbe/DOCSIS 3.0 256-QAM 대비 약 30% 전송효율이 개선된 3D/8K-UHDTV 대용량 실감미디어 콘텐츠 전송을 위한 방송망 채널결합형 1024-QAM 송수신기 구현 및 개발에 관한 내용을 기술한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.574-577
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• 2011

H.264/AVC는 휘도 신호 $4{\times}4$ 블록을 위하여 9개의 화면 내 예측모드를 사용한다. 예측 모드는 8개의 방향성을 가진 모드와 하나의 비방향성 DC 모드가 있다. 휘도 신호 $16{\times}16$ 블록에서는 4가지의 예측 모드가 있으며 색차 신호 $8{\times}8$ 에서도 4개의 예측모드를 사용한다. 이러한 예측 모드들 중 최적의 예측 모드를 선택하기 위하여, 부호화기는 선택 가능한 모든 예측 모드의 율-왜곡 비용을 계산한 후, 최적의 율-왜곡 비용을 가진 예측 모드를 사용하여 부호화를 수행한다. 따라서 H.264/AVC의 화면 내 예측 과정은 많은 계산 복잡도를 가진다. 특히 하이 프로파일에서는 휘도 신호 $8{\times}8$ 블록이 화면 내 예측을 위해서 고려되므로 더욱 많은 계산 복잡도를 요구한다. 이에 본 논문은 H.264/AVC 하이 프로파일의 화면 내 예측의 부호화 계산 복잡도를 줄이는 방법을 제안한다. 현재 매크로 블록의 분산을 계산한 후, 이를 이용하여 율-왜곡 최적화에 후보로 사용되어지는 블록 모드를 결정하고, 각 블록 모드에서 제공하는 예측 모드들을 효율적으로 선택하는 방법을 연구 개발하였다. 제안된 방법은 기존 H.264/AVC 참조 소프트웨어인 JM13.1 부호화 시간 대비 약 83%의 연산시간이 감소하는 결과를 보였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.113-116
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• 2004

T-DMB 서비스의 경우 무시할 수 없는 빈도로 자주 전송 오류가 발생할 가능성이 있으므로, 내부 비디오 코덱인 H.264/AVC는 이 전송 오류에 의한 영향을 극복하기 위한 방안을 갖추도록 설계되어야 한다. 본 논문은 이 경우에 대비하여, 오류 내성이 있는 새로운 부호화 모드 결정 기법을 제안한다. WCDMA 채널을 통한 전송 시뮬레이션을 통하여, 제안하는 부호화 모드 결정 기법을 적용하는 경우 오류 내성을 고려하지 않고 부호화 모드를 결정하는 경우에 비해서 고-복잡도의 경우에는 평균적으로 0.77dB, 저-복잡도의 경우에는 0.35dB의 재생화질 개선 효과가 있음을 보였다. 고-복잡도 부호화 모드 결정 기법의 경우는 H.263에서 제시된 고-복잡도 부호화 모드 결정 기법에 비해서 평균적으로 0.l1dB 개선된 값이다.