• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.199-206
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• 2004

Under the multiprogrammed situation, the performance of multiprocessor system is affected by the process allocation policy of the operating systems. The lowest communication cost can be achieved when the related processes positioned to the adjacent processors. While the effective allocation is quite difficult to the real situation, and the processing of the allocation policy consumes some computation time. The dual-ring CC-NUMA systems exhibit a quite performance difference according to the process a1location policy due to a lot of unbalanced memory transactions on the interconnection networks. In this paper, I propose a load balanced dual-link CC-NUMA system that does not requires the processes allocation policy. By the program-driven simulation results. the proposed system shows no remarkable difference according to the allocation policy while the dual-ring systems shows 10％ performance improvement by the process allocation. In addition, the proposed system outperforms the dual~ring systems about 1.5 times.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Journal of Korea Multimedia Society
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• v.3 no.3
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• pp.309-319
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• 2000

The purpose of a parallel scheduling under a multiprocessor environment is to carry out the scheduling with the minimum synchronization overhead, and to perform load balance for a parallel application program. The processors calculate the chunk of iteration and are allocated to carry out the parallel iteration. At this time, it frequently accesses mutually exclusive global memory so that there are a lot of scheduling overhead and bottleneck imposed. And also, when the distribution of the parallel iteration in the allocated chunk to the processor is different, the different execution time of each chunk causes the load imbalance and badly affects the capability of the all scheduling. In the paper. we investigate the problems on the conventional algorithms in order to achieve the minimum scheduling overhead and load balance. we then present a new parallel loop scheduling algorithm, considering the locality of the data and processor affinity.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.499-510
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• 2004

This paper proposes a heuristic load balancing algorithm for multiprocessor systems. The algorithm minimizes the number of idle links to distribute load traffic and reduces its communication cost. Each processor iteratively tries to transfer unit load to/from every neighbor processors. However, real load transfer is collectively done after complete load traffic calculation to minimize useless traffic. The proposed algorithm can be employed in various interconnection topologies with slight modifications. In this paper, it is applied to both hypercube and mesh environments. For performance evaluation, simulation studies are performed. The performance of proposed algorithm is compared to those of two well-known algorithms. The results show that the proposed algorithm always balances the loads perfectly. Furthermore, it reduces the communication costs by $70{\%}{\~}90{\%}$ in the hypercube ; and it reduces the cost by $\75{\%}$ in the mesh, compared to existing algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.3
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• pp.144-154
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• 2001

다중 결합 질의에 포함된 다수의 결합 연산지를 효율적으로 처리하기 위해 서는 효율적인 병렬 알고리즘이 필요하다. 최근 다중 해쉬 결합 질의의 처리를 위해 할당 트리를 이용한 방법이 가장 우수한 것으로 알려져 있다. 그러나 이 방법은 실제 결합 시에 할당 트리의 각 노드에서 필연적인 지연이 발생되는 데 이는 튜플-시험 단계에서 외부 릴레이션을 디스크로부터 페이지 단위로 읽는 비용과 이미 읽는 페이지에 대한 해쉬 결합 비용간의 차이에 의해 발생하게 된다. 이들 사이의 실행시간을 가급적 일치시키기 위한 '페이지 실행시간 동기화'기법이 제안되었고 이를 통해 할당 트리 한 노드 실행에 있어서의 지연 시간을 줄일 수 있었다. 하지만 지연 시간을 최소화하기 위해 할당되어질 프로세서의 수 즉, 페이지 실행시간 동기화 계수(k)는 실제 결합 시의 결합률에 따라 상당한 차이를 보이게 되고 결국, 이 차이를 고려하지 않은 다중 해쉬 결합은 성능 면에서 크게 저하될 수밖에 없다. 본 논문에서는 결합 이전에 어느 정도의 결합률을 예측할 수 있다는 전제하에 다중 해쉬 결합 실행 시에 발생할 수 있는 지연 시간을 최소화 할 수 있도록 결합률에 따라 최적의 프로세서들을 노드에 할당함으로서 다중 해쉬 결합의 실행 성능을 개선하였다. 그리고 분석적 비용 모형을 세워 기존 방식과의 다양한 성능 분석을 통해 비용 모형의 타당성을 입증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.40-48
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• 2015

This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1785-1796
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• 1993

Thanks to the data processing facilities of modern digital computers, the performances of radar has been promoted greatly as one of the main components of command and control systems along with the computer communications. In this study, radar data integrating and processing systems were designed for the data processing of various information from many kinds of radar in a single data processing system. The performance of the data integrating system was analyzed by applying queueing theory. A radar data integrating network was designed for synchronous relational operations among the information processing systems and the transmission characteristics were also analysed by specific models for each system. The designed data integrating systems can be divided into a simplex type and a distributed multiplex type.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.461-476
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• 2003

Due to the implementation ease and alleviation of memory bottleneck effect, NUMA architecture has dominated in the multiprocessor systems for the past several years. However, because the NUMA system distributes memory in each node, frequent remote memory access is a key factor of performance degradation. Therefore, efficient design of RAC(Remote Access Cache) in NUMA system is critical for performance improvement. In this paper, we suggest Multi-Grain RAC which can adaptively control the RAC line size, with respect to each application behavior Then we simulate NUMA system with multi-grain RAC using MINT, event-driven memory hierarchy simulator. and analyze the performance results. At first, with profile-based determination method, we verify the optimal RAC line size for each application and, then, we compare and analyze the performance differences among NUMA systems with normal RAC, with optimal line size RAC, and with multi-grain RAC. The simulation shows that the worst case can be always avoided and results are very close to optimal case with any combination of application and RAC format.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.111-113
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• 1998

공간조인은 지리정보 시스템에서 공간분석을 위한 주요 연산중의 하나이다. 이러한 공간조인은 대상이 되는 공간 객체의 수가 증가함에 따라 연산시간이 지수적으로 증가하는 특징을 가지고 있다. 그래서 대규모 공간 데이터에 다한 공간 연산시간을 줄이기 위한 처리기법이 연구되고 있다. 그렇지만, 공유 디스크 구조에서 다중 프로세서의 디스크 동시 접근으로 인한 병목현상을 완화하고, 프로세서간의 공유 디스크 구조에서 다중 프로세서의 디스크 동시 접근으로 인한 병목현상을 완화하고, 프로세서간의 메시지 전달을 최소화하기 위한 태스크 생성방법, 태스크 할당방법에 관한 구체적인 연구가 없었다. 그래서 우선 병렬 공간 조인의 성능저하 요인을 분석하고, 이에 대한 성능 향상방안을 제시한다. 구체적으로 디스크 접근 시간을 줄이기 위한 객체 캐쉬 방법과 시공간 지역성을 이용한 태스크 생성 및 할당방법을 제시한다. 그리고 제안한 방법들에 대해 실험평가를 통해 최대 7.2배의 성능증가를 획득할 수 있음을 보여준다.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.383-392
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• 2000

Currently, multiprocessors are evaluated almost exclusively with scientific applications. Commercial applications are rarely explored because it is difficult to obtain the source codes of commercial DBMS. Even when the source code is available, such as for POSTGRES, understanding the source code enough to perform detailed meaningful performance evaluations is a daunting task for computer architects.To evaluate multiprocessors with commercial applications, we have developed our own DBMS, called EZDB. EZDB is a parallelized DBMS, loosely inspired from POSTGRES, and running on top of a software architecture simulator. It is capable of executing parallel programs written in SQL. Contrary to POSTGRES, EZDB is not intended as a prototype for a production-quality DBMS. Its purpose is to easily run and evaluate the performance of commercial applications on multiprocessor architectures. To illustrate the usefulness of EZDB, we showed the cache performance data collected for the TPC-B benchmark on a shared-memory multiprocessor. The simulation results showed that the data structures exhibited unique sharing characteristics and that their locality properties and working sets were very different from those in scientific applications.