• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 2004.04a
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• pp.509-513
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• 2004

현장 균열망의 연결성 및 이에 따른 수리지질학적 특성을 규명하기 위하여, 기존의 통상적인 조사 기법을 한 지역에 집적하여 그 결과에 대한 통합해석을 수행하였다. 본 연구에 적용된 조사 방법은 양수시험, 물리검층, 다중심도 수리화학 분석, 전기비저항 토모그래피, 시추 코어 검층 등의 기련 특성 조사와, 추적자 시험, 다중 심도 수직 유향유속 시험 등 구간별 특성 조사 등이다. 이러한 조사 결과 본 조사 지역 내 균열의 전반적인 분포 특성을 확인할 수 있었으며, 각 균열의 수리적 특성에 대한 기본적 특성을 확인할 수 있었다. 특히 추적자 시험과 유향유속 시험 결과를 통해 각 관정간의 균열을 통한 연결성에 대한 중요한 정보를 도출할 수 있었다. 이러한 성과는 추후 percolation, connectivity 등 모델 개념의 현장화를 위한 연구의 선행 연구로서 그 의미를 자리매김 할 수 있을 것이다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.72-79
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• 2011

The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.258-273
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• 2011

This paper designs and implements a multi-view 3D video player system which is operated faster than existing video player systems. The structure for obtaining the near optimum speed in a multi-processor environment by parallelizing the component modules is proposed to process large volumes of multi-view image data at high speed. In order to use the concurrency of bottleneck, we designed image decoding, synthesis and rendering modules in a pipeline structure. For load balancing, the decoder module is divided into the unit of viewpoint, and the image synthesis module is geometrically divided based on synthesized images. As a result of this experiment, multi-view images were correctly synthesized and the 3D sense could be felt when watching the images on the multi-view autostereoscopic display. The proposed application processing structure could be used to process large volumes of multi-view image data at high speed, using the multi-processors to their maximum capacity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.294-295
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• 2005

다중 코어를 이용한 대전류 변압기용 Mn-Zn ferrite를 제조하고 전자기적 특성을 분석하였으며, 제조된 자심재료를 이용하여 변압기를 제조하고 전원장치에 탑재하여 효율특성을 분석하였다. ZnO의 몰비가 증가할수록 혼합 스피넬의 형성을 통한 보아 자자의 증가로 인해 투자율은 증가하고 상대적으로 전력손실이 감소하여 $Fe_2O_3$ : MnO : ZnO = 53 : 36 : 11 mo\% 일 때 가장 우수한 특성을 나타냈고, 열처리 공정의 승온 과정에서부터 산소 분압을 제어하고 최적의 대기압 상수를 산출함으로써 Zn-loss 현상을 최소화하여 ZnO 11 mol%, 대기압 상수 7.7일 때 투자율 2350, 밀도 4.9 $g/cm^3$, 비저항 480 ${\Omega}cm$, 300 mT의 최대 자속 밀도 특성을 갖는 우수한 자심 재료를 개발하였다. 그리고 최소 손실 온도를 $90^{\circ}C$ 이하로 감소시켰으며 100 kHz에서 250 $kW/m^3$의 낮은 전력손실을 나타냈다. 또한 개발된 자심재료를 이용하여 제조된 전원장치는 30~80A의 출력 전류에서 85% 이상의 고효율을 얻었다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.85-90
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• 1998

A 1 4 polymeric optical power divider based on the multimode interference effect is designed and fabricated. The two dimensional finite difference beam propagation method has been utilized in designing the device. Polymers used for the core layer and the cladding layer are Cyclotene-3022 and UV-15, respectively. The device is fabricated by the reactive ion etching method. The splitting ratio of the fabricated device is 0.93 : 1.00 : 0.93 : 0.90 for TE mode and 0.84 : 0.94 : 1.00 : 0.83 for TM mode. The advantages of this device are small size and low polarization-dependence.

• Korean Journal of Optics and Photonics
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• v.9 no.1
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• pp.25-30
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• 1998

In this paper, a simple scheme of optical interconnections between M input and N output terminals using mode speckle patterns generated in the mulitmode optical fiber is described. It is shown that fully parallel nonblocking interconnections are accomplished by using properly generated mode speckle patterns as destination codes and dectecting the generated mode speckle patterns separately using M multiplexed Vander Lugt matched filters at each output terminal. The orthogonality condition of mode speckle patterns is investigated by either changing the launching angles or rotating the polarization direction of the beam. Preliminary experiments by use of a 4$\times$4 graded refractive-index multimode fiber coupler whose core diameter was 50 ${\mu}{\textrm}{m}$ were performed to show the feasibility of our scheme.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.9
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• pp.799-804
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• 2016

Broadband powerline communication (BPLC) uses distribution lines as a medium for achieving effective bidirectional data communication along with electric current flow. As the material characteristics of power lines are not good at the communication channel, the development of power line communication (PLC) systems for internet, voice, and data services requires measurement-based models of the transfer characteristics of the network suitable for performance analysis by simulation. In this paper, an analytic model describing a complex transfer function is presented to obtain the attenuation and path parameters for a multipath power line model. The calculated results demonstrated frequency-selective fading in multipath channels and signal attenuation with frequency, and were in good agreement with the experimental results. Inductive coupling units are used as couplers for coupling the signal to the power line to avoid physical connections to the distribution line. The inductance of the ferrite core, which depends on the frequency, determines the cut-off frequency of the inductive coupler. Coupling loss can be minimized by increasing the number of windings around the coupler. Coupling efficiency was improved by more than 6 dB with three windings compared to the results obtained with one winding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.885-892
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• 2013

In the model Utilizing the TCP / IP socket communication to transmit and receive data, if the size of data is small and if data-transmission aren't frequently requested, the importance of communication speed between a server and a client isn't emphasized. But nowadays, it has emerged for large amounts of data transfer requests and frequent data transfer request. This paper propose the TCP/IP communication model that can be improved the data transfer rate in multi-core environment by changing the receiving structure of the client to receive large amounts of data and the transmission structure of the server to send large amounts of data.

• Journal of KIISE:Software and Applications
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• v.27 no.8
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• pp.795-803
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• 2000

This paper presents a shared data decomposition model for improving concurrency in multi-user, distributed software developments. In our model, the target software system is decomposed into the independent components based on project roles to be distributed over clients. The distributed components are decomposed into view objects and core objects to replicate only view objects in a distributed collaboration session. The core objects are kept in only one client and the locking is used to prevent inconsistencies. The grain size of a lock is a role instead of a class which is commonly used as the locking granularity in the existing systems. The experimental result shows that our model reduces response time by 12${\sim}$18% and gives good scalability.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.421-422
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• 2020

Hardware In-the-Loop simulation(HIL)은 실제 하드웨어 시스템을 실시간 모사할 수 있는 시뮬레이션 장비로 연구 및 개발 기간의 단축, 비용저감 등의 장점을 앞세워 다양한 전력전자 분야에 사용되고 있다. 실제 하드웨어를 그대로 모사하는 것이 HIL의 목적이기 때문에 HIL 장비는 검증의 실시간성과 출력된 결과의 정확성이 무엇보다도 중요하다고 할 수 있다. 하지만 코어간의 데이터를 주고받는 과정에서 HIL의 연산 속도 및 정확성을 저해하는 요인들이 발생하게 된다. 본 연구에서는 HIL 장비를 이용해 복잡한 시스템을 구현함에 있어서 연산속도 및 정확성을 저해하는 요인들을 찾아내고 이를 해결하기 위한 방법을 제안한다. 제안된 연산속도 개선 및 정확성 개선 방법의 타당성은 프로세서의 연산 속도 변화량, HIL 및 시험 결과 파형의 비교 분석을 통해 검증되었다.