• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.482-489
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• 2010

In this paper we have proposed a new architecture of DQ-IRM(Double-Quadrature Image Rejection Mixer) for image rejection in the low-IF receiver. It consist of a frequency-tunable RF PPF(Poly Phase Filter) and the quadrature mixers. The conventional DQ-IRM generates the quadrature RF signals for the RF wide band at once. But the proposed DQ-IRM with the frequency-tuable RF PPF generates the quadrature RF signals for the narrow band of 2~3 channels bandwidth, which is partitioned from the RF wide band. We designed the CMOS RF tuner for T-DMB(Terrestrial Digital Multimedia Broadcasting) with the proposed 3rd DQ-IRM using a 0.18um CMOS technology and verified the performances of the designed receiver such as the image rejection ratio, the noise figure and the power consumption. The overall NF of the RF tuner is about 1.26 dB and the image reject ratio is about 51 dB. The power consumption is 55.8 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.1
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• pp.15-19
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• 2005

Conventional eddy current testing has been used for the detection of the defect-like fatigue crack in the conductive materials, such as aluminum, which uses a sinusoidal signal with very narrow frequency bandwidth, Whereas, the pulsed eddy current method uses a pulse signal with a broad bandwidth. This can allow multi-frequency eddy current testing, and the penetration depth is greater than that of the conventional eddy current testing. In this work, a pulsed eddy current instrument was developed for evaluating the metal loss. The developed instrument was composed of the pulse generator generating the maximum square pulse voltage of 40V, an amplifier controlled up to 52dB, an A/D converter of 16 bit and the sampling frequency of 20 MHz, and an industrial personal computer operated by the Windows program. A pulsed eddy current probe was designed as a pancake type in which the sensing roil was located inside the driving roil. The output signals of the sensing roil increased rapidly wich the step pulse driving voltage かn off, and the latter part of the sensing coil output voltage decreased exponentially with time. The decrement value of the output signals increased as the thickness of the aluminum test piece increased.

• Journal of Sensor Science and Technology
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• v.7 no.3
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• pp.154-162
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• 1998

A planar Bi-Sb multijunction thermal converter with high thermal sensitivity and small ac-dc transfer error has been fabricated by preparing the bifilar thin film Pt-heater and the hot junctions of thin film Bi-Sb thermopile on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$-diaphragm, which functions as a thermal isolation layer, and the cold junctions on the dielectric membrane supported with the Si-substrate, which acts as a heat sink, and its ac-dc transfer characteristics were investigated with the fast reversed dc method. The respective thermal sensitivities of the converter with single bifilar heater were about 10.1 mV/mW and 14.8 mV/mW in the air and vacuum, and those of the converter with dual bifilar heater were about 5.1 mV/mW and 7.6 mV/mW, and about 5.3 mV/mW and 7.8 mV/mW in the air and vacuum for the inputs of inside and outside heaters, indicating that the thermal sensitivities in the vacuum, where there is rarely thermal loss caused by gas, are higher than those in the air. The ac-dc voltage and current transfer difference ranges of the converter with single bifilar heater were about ${\pm}1.80\;ppm$ and ${\pm}0.58\;ppm$, and those of the converter with dual bifilar heater were about ${\pm}0.63\;ppm$ and ${\pm}0.25\;ppm$, and about ${\pm}0.53\;ppm$ and ${\pm}0.27\;ppm$, respectively, for the inputs of inside and outside heaters, in the frequency range below 10 kHz and in the air.

• Journal of radiological science and technology
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• v.38 no.2
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• pp.121-126
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• 2015

To image diagnosis in neurovascular diseases using Multi-Detector Computed Tomography(MDCT), injected the same contrast material when inspecting Brain Computed Tomography Angiography(BCTA) to examine radiation dose and Image quality on changing Cerebral Artery CT number by tube voltage. Executed an examination with same condition[Beam Collimation $128{\times}0.6mm$, Pitch 0.6, Rotation Time 0.5s, Slice Thickness 5.0mm, Increment 5.0mm, Delay Time 3.0sec, Care Dose 4D(Demension ; D)] except for tube voltage on 50 call patients for BCTA and divided them into two groups (25 people for a group, group A: 80, group B: 120kVp). From all the acquired images, set a ROI(Region of Interest) on four spots such as left cerebral artery, right cerebral artery, posterior cerebral artery and cerebral parenchyma to compare quantitative evaluation, qualitative evaluation and effective dose after measuring CT number value from Picture Archiving Communications System(PACS). Evaluating images with CT number acquired from BCTA examination, images with 80 kVp was 18% higher in Signal to Noise Ratio and 19% in Contrast to Noise Ratio than those with 120 kVp. It was seen that expose dose was decreased by over 50% with tube voltage 80 kVp than with 120 kVp. Group A (25 patients) was examination with tube voltage 80kVp while group B with 120 kVp to examine radiation dose and Image quality. It is considered effective to inspect with lower tube voltage than with conventional high kVp, which can reduce radiation dose without any affect on diagnosis.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.1
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• pp.5-10
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• 2012

In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.