• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.83-96
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• 2005

The multichannel switch is an architecture widely used for ATM (Asynchronous Transfer Mode). It is known that the fault tolerant characteristic can be incorporated into the multichannel crossbar switching fabric. For example, if a link belonging to a multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if a fault occurs in a switching element, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithm in multichannel crossbar ATM switches with a view to early fault recovery. The optimal algorithm gives the best performance in terms of time to localization but it is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally more efficient than the optimal one. We evaluate its performance through simulation. The simulation results show that the Performance of the on-line algorithm is only slightly sub-optimal for both random and bursty traffic. There are cases where the proposed on-line algorithm cannot pinpoint down to a single fault. We enumerate those cases and investigate the causes. Finally, a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm The fault recovery algorithm providesadditionalrowsandcolumnstoallowcellstodetourthefaultyelement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.561-563
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• 2000

본 논문은 멀티캐스트 패킷 스위치의 성능 향상에 관하여 언급한다. 네트워크에 요구된 복사본의 수가 네트워크의 크기보다 클 경우 발생되는 오버플로우 문제를 해결하기 위해 Lee의 브로드캐스트 반얀 네트워크(BBN)를 기반으로 하여 다중경로와 다중출력을 제공하는 기능이 추가된 구조를 제안하였으며, 여기에 입력에서 다음 처리해야할 패킷의 fanout 값이 남아있는 BBN의 출력포트 수보다 클 경우 패킷이 복사될 수 없게됨으로서 발생되어질 수 있는 네트워크의 성능이 저하되는 문제를 해결하기 위하여, 셀분할 알고리즘을 이용한 수정된 DAE(dummy address encoder) 방식을 제안하였다.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.73-78
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• 2004

There are random, continuous, and periodic allocation methods in the time slot sequence integrity for the multi-slot call. In the T-S-T switch, there are 2 time switch and the 2*2 space switch. Three time-slot allocation methods are suggested for the simulation. In the simulation, the searching times for time-slots on a multi-slot call is chosen to 32, and the simulation time is chosen to 100,000 seconds. Three kinds of calls are supposed for a multi-slot call : one time-slot call, two time-slot call, and 6 time-slot call. In the simulation, the carried traffic and the blocking probability are calculated on the 3 different traffic cases of 8:1:1, 6:2:2, 4:3:3(one time-slot : two time-slot : 6 time-slot) multi slot calls. It is shown that the blocking probability for the periodic time slot allocation method is best. As a result, the periodic time-slot allocation method is the proper one for the multi-slot ATM switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.7B
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• pp.1236-1243
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• 2000

본 논문은 LAN의 대역폭을 증가 시키기 위하여, 여러 개의 링크를 논리적인 하나의 링크처럼 동작하도록 하는 다중링크통함(link aggregation)기술에 대한 것이다. 우리는 망 구성에 따라 이 기술의 동작방식이 상이함에 착안하여, 두 가지의 새로운 프레임 분배방식을 제안하고 SIMULA를 이용한 모의실험으로 성능을 분석하였다. 먼저, LAN스위치와 스위치간에 적용 가능한 동적 프로엠 분배방식을 제안하였다. 이 방식은 특정 포트로 집중되는 프레임들을 분산시키기 위하여 가장 이용율이 낮은 링크를 동적으로 추가하는 것으로서, 링크 추가시 프레임들의 전달순서를 지킬 수 있도록 특별한 플러쉬 버퍼를 사용하였다. 모의실험 결과, 프러임간의 순서가 유지되면서도 스위치의 내부 버퍼에서의 프레임 폐기율이 기존 방식에 비해 감소됨을 확인하였다. 그리고, 단말과 단말간에 다중링크가 사용된 경우, 수신된 프레임들 간의 순서 뒤바뀜 문제에 대한 해결책으로 패딩 방법과, 태깅 방법, 프레임 분할 방식 등의 세가지으 프레임 분배방식을 제안하고 성능을 분석하였다. 이러한 세가지 방법 중에서 프레임 분할방식이 가장 성능면에서 우수함이 모의실험결과\ulcorner서 알 수 있지만, 패딘 방식도 구현관점에서 장점이 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1300-1312
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• 1991

In this paper we syudy the time slot sequence integrity(TSSI) of multi-slot calls in the single-buffered switching networks and analyze their traffic characteristics in terms of traffic mixture ratio, number of random searches for idle time slots, and their blocking probablities. This result can be utilized in the design of wideband switching networks in the single buffered systems, such as TDX IA/B swithcing systems, for accommodating multi slot calls.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1143-1153
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• 1991

In this paper, we proposed a new ATM switch structure which is based on the GAMMA network, proving multipath between an input and an output port. The size of the proposed new ATM switch will be smaller than the switches based on the BANYAN network, which includes the Sorting network to resolve the blocking in the switch fabric. Also, the validity and the utility of the proposed switch structure is verified through a simulation method.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.518-519
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• 2014

선형 유도 전동기 구동 인버터의 스위치 결함에 대한 신뢰성 향상을 위해, 실제 온라인 기반의 고장 및 고장점 검출에 대한 연구가 활발하다. 인버터에서 스위치 고장이 발생하면, 일반적으로 전압, 전류에 고조파가 발생되고 토크의 리플이 증가하게 된다. 또한, 인버터 스위치 고장의 경우 과전류가 발생하며 다른 전자 부품에 2차 피해를 일으킬 수 있다. 본 논문에서는 센서를 통해 얻은 전류의 정보를 이용하여 고장 및 고장 스위치를 검출하는 알고리즘을 제안한다. 한 개 또는 두 개의 스위치 고장을 4개의 faulty group으로 구별하여 고장 검출이 이루어지며 제안된 알고리즘을 입증하기 위해 Matlab-Simulink을 이용한 시뮬레이션 결과와 실험 결과가 제시된다.