• Journal of Internet of Things and Convergence
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• v.9 no.3
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• pp.81-86
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• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.907-916
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• 2019

In this paper, we propose a new five-qubit multiple bit flip code that can completely protect the target qubit from all multiple bit flip errors using only CNOT gates. The proposed multiple bit flip codes can be easily extended to multiple phase flip codes by embedding Hadamard gate pairs in the root error section as in conventional single bit flip code. The multiple bit flip code and multiple phase flip code in this paper share the state vector error information by four auxiliary qubits. These four-qubit state vectors reflect the characteristic that all the multiple flip errors with Pauli X and Z corrections commonly include a specific root error. Using this feature, this paper shows that low-cost implementation is possible despite the QECC design for multiple-flip error correction by batch processing the detection and correction of Pauli X and Z root errors with only three CNOT gates. The five-qubit multiple bit flip code and multiple phase flip code proposed in this paper have 100% error correction rate and 50% error discrimination rate. All QECCs presented in this paper were verified using QCAD simulator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.68-71
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• 2012

본 논문은 운영 체제(Operating System)에서 수행되는 프로세스(Process)의 가상 주소 공간(Virtual Address Space)을 기존의 단일 가상 주소 공간에서 다중 가상 주소 공간으로 확장시켜서, 하나의 프로세스가 기존보다 더욱 넓은 가상 메모리 영역을 쉽게 사용할 수 있도록 해주는 방안을 제안한다. 최근 컴퓨팅 기기들은 비약적으로 증가한 메모리를 쉽게 사용할 수 있는 수단이 필요하다. 최근 PAE(Physical Address Extension)를 지원하는 32 비트 프로세서나 32 비트 명령어를 같이 지원하는 64비트 프로세서들은 프로세스의 가상 주소 크기보다 더욱 큰 용량의 메모리를 사용할 수 있어서, 한 프로세스가 장착된 메모리의 일부분 밖에 사용할 수 없는 일이 발생한다. 이를 해결하기 위해서 64비트 프로세서의 경우 64-비트 명령어를 사용하지만 이는 프로그램의 명령어 크기나 포인터 변수 크기의 증가로 메모리 사용량을 크게 늘릴 수 있어서 서버 컴퓨터나 데스크탑 PC 와 같이 충분한 양의 메모리를 장착한 시스템에서만 효과적이다. 본 논문에서 제안하는 다중 주소 공간을 지원하는 프로세스는 모바일 및 임베디드 기기와 같이 상대적으로 제한된 용량의 메모리를 지원하는 시스템에 유용할 것으로 기대한다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.749-755
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• 2003

Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.87-90
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• 2010

본 논문에서는 무선 방송 환경에서 XML에 대한 다양한 사용자 질의에 대하여 다중 채널을 통해 효과적으로 질의의 결과를 전송하기 위한 색인 기법을 고려한다. 이를 위해 서버측에서는 질의 결과뿐만 아니라 원본 XML상에서 질의 결과가 위치하는 계층 정보까지 파악이 가능한 비트 좌표 기반 색인 기법을 제안한다. 제안 기법의 시뮬레이션을 통해 다중 채널의 효과뿐만 아니라 색인으로 인해 빠른 응답시간을 가짐을 보인다.

• The Journal of the Acoustical Society of Korea
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• v.23 no.3
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• pp.262-267
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• 2004

AMR-WB (Adaptive Multi Rate Wideband) speech codec, the most recent voice codec standardized by 3GPP, has the wider audio bandwidth of 50∼7000 Hz and operates on nine speech coding bit rates between 6.60 and 23.85 kbit/s. This Paper presents the real-time implementation of AMR-WB speech codec by using a 16 bit fixed-point TeakLite DSP. The implemented AMR-WB codec requires the complexity of 52.2 MIPS at 23.85 kbit/s mode and also needs the program memory of 17.9 kwords, data RAM of 11.8 kwords, and data ROM of 10.1kwords. It was verified through passing the all test vectors provided by 3GPP with maintaining bit exactness. Stable operations on the real-time testing board were also proved without any distortions and delays for the audio in/out.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10b
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• pp.209-211
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• 1999

본 논문에서는 저가형 멀티미디어 시스템 제작에 대해서 소개한다. 본 시스템은(DigiAlbum)은 정지 영상과 동영상을 출력, 수정, 저장이 가능하며, 사용자가 쉽게 이용할 수 있도록 리모콘으로 작동하게 되어 있다. DigiAlbum은 IBM 호환형태의 STPC CPU를 사용하였고, PCMCIA를 사용하였다. 멀티미디어 전용 단일 사용자 다중처리 32비트 Mini OS를 탑재하였으며, 정규 비트맵 메모리 블록을 이용한다. 어플리케이션 프로그램은 하드웨어를 직접 제어하며, 비디오 메모리 직접 엑세스와 Fast DCT를 이용하여 빠른 영상 복호/부호화를 처리한다. 멀티미디어 처리 부분에서 DigiAlbum은 일반 고가형 PC급과 그 성능이 같다.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.877-882
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• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor because of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2005.10a
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• pp.37-42
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• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor bemuse of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.