• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1145-1148
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• 1999

본 논문은 다중마스터 시스템의 버스 공유를 큐잉이론으로 모델링하여 정량화하고 이를 바탕으로 최적화 된 실시간 시스템을 설계하는 방법을 제안하였으며 그 결과를 실측 실험을 통해서 검증하였다. 다중마스터 모드와 슬레이브 모드를 지원하는 마스터를 이용한 다중 마스터 시스템에서 버스의 공유로 인한 지연과 각 작업의 대기 시간은 각각에 대한 모델링을 통해 정량화 할 수 있으며 이를 통하여 최적화된 시스템을 구성할 수 있게 된다. 본 논문의 실험에서는 VMEbus 상에서 3개의 마스터와 그에 종속된 4개의 슬레이브 시스템을 구성하여 각 마스터들의 버스 요구율과 서비스 시간에 따라 버스를 점유하기 위해 기다리는 시간을 정량적으로 분석하였으며 이를 통하여 개선된 시스템은 각 작업의 버스 상에서의 대기 시간을 최소화하고 효과적으로 버스를 공유하므로써 작업 시간 오차와 오류 발생을 최소화 할 수 있음을 보였다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1992.11a
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• pp.81-98
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• 1992

본 논문에서는 TRM을 이용한 사용자의 ID를 기초로 하는 암호시스템을 구현하고 안전성 유지를 위해 반드시 필요한 TRM과 사용자사이의 쌍방인증방식을 설명하였다. 그리고 이의 개선된 방식으로서 키 생성키인 마스터키를 다중화 하여 TRM내에 국소 분배함으로써 TRM내의마스터 키를 시스템 상에서 보호하는 방안과 TRM Identity(TID)를 이용한 디지탈 서명방식을 제안하였다. 제안된 방식은 암/복호화의 속도가 빠른 관용 암호알고리듬을 사용하면서도 디지탈 서명을 비롯한 공개키 암호알고리듬이 가지고 있는 장점들을 모두 구현하고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.74-80
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• 2012

Recently at SCIS2011, Nakatsu et. al. proposed multi-round Correlation Power Analysis(CPA) on Hardware Advanced Encryption Standard(AES) to improve the performance of CPA with limited number of traces. In this paper, we propose, Multi-Round CPA to retrieve master key using CPA of 1round and 2round on Hardware DES. From the simulation result for the proposed attack method, we could extract 56-bit master key using the 300 power traces of Hardware DES in DPA contes. And it was proved that we can search more master key using multi-round CPA than using single round CPA in limited environments.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.177-182
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• 1998

This paper proposes pure master key which can be commonly used in multi-cryptographic system. It also refer to master key condition for RSA public key cryptosystem using Format's theorem and master key algorithm as well.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• KIISE Transactions on Computing Practices
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• v.21 no.11
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• pp.699-705
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• 2015

Thousands of glyphs are necessary for Hangul font generation. It is mandatory to generate the required glyphs before producing Hangul font. This paper, entitled "Multiple Master Glyph Algorithm", presents an process that generates a target number of glyphs automatically from a very small number of glyphs by using a combination rule setting and a glyph interpolation method. A font editor, which is able to generate Hangul glyphs or fonts, is developed based on this algorithm. The editor generates a target number of fundamental glyphs automatically by using a combination rule setting and four master glyphs, which can be set up by a user. The automatically generated glyphs can be used to generate a target font by combining KSX1001 standard Hangul 2350 characters or Unicode standard Hangul 11172 characters automatically. The efficiency of the proposed Hangul editor is analyzed quantitatively in this paper through application to several commercial typefaces.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.369-370
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• 2007

본 논문에서는 IDLE 전송만을 수행하거나 버스접근빈도가 낮은 디폴트 마스터(Default Master)를 버스에 대한 접근빈도가 가장 높은 마스터로 재정의 하고, 버스접근빈도가 가장 높은 마스터를 찾기 위한 블록을 제작하여 추가하였다. 이 블록을 이용하여 버스에 대한 접근빈도와 데이터의 특성에 따라 디폴트 마스터를 재설정 해줄 수 있다 이로써 버스에 대한 접시간을 줄이고, 다중버스구조에서 단일버스구조와 동일한 전송이 가능하게 하여, 기존의 디폴트 마스터를 사용한 버스 구조에서 보다 효율적인 전송이 가능하다.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.11
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• pp.471-478
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• 2014

Database replication is utilized to increase credibility, availability and prevent overload of distributed databases. Two models currently exist for replication - Master/Slave and Multi-Master. Since the Multi-Master model has problems of increasing complexity and costs to interface among multiple databases for updates and inserts, the Master/Slave model is more appropriate when frequent data inserts and updates are required. However, Master/Slave model also has a problem of not having exact criteria when systems choose to connect between Master and Slave for transactions. Therefore, this research suggests a routing algorithm based on AOP (Aspect Oriented Programming) in the Master/Slave database model. The algorithm classifies applications as cross-cutting concerns based on AOP, modularizes each concern, and routes transactions among Master and Slave databases. This paper evaluates stability and performance of the suggested algorithm through integration tests based on scenarios.