• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.1
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• pp.378-384
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• 2013

In this paper, we propose the fuzzy neural networks based on fuzzy c-means clustering algorithm. Typically, the generation of fuzzy rules have the problem that the number of fuzzy rules exponentially increases when the dimension increases. To solve this problem, the fuzzy rules of the proposed networks are generated by partitioning the input space in the scatter form using FCM clustering algorithm. The premise parameters of the fuzzy rules are determined by membership matrix by means of FCM clustering algorithm. The consequence part of the rules is expressed in the form of polynomial functions and the learning of fuzzy neural networks is realized by adjusting connections of the neurons, and it follows a back-propagation algorithm. The proposed networks are evaluated through the application to nonlinear process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1648_1649
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• 2009

BLDC는 낮은관성, 빠른응답, 높은 전력밀도, 높은 신뢰성 및 유지보수를 요구하지 않기 때문에 산업용 어플리케이션에 널리 이용되고 있다. BLDC는 종래의 영구자석 DC모터의 운영 특성을 보이고 있지만 기계적인 정류자와 브러쉬를 제거 하였다. BLDC의 경우 자속이 일정하기 때문에 속도 제어가 중요하다. 회전자의 속도를 제어하기 위해 전류 지령치를 퍼지 뉴럴 네트워크를 이용하여 제어치를 추정한다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.504-509
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• 1995

컴퓨터에 의한 생산시스템의 통합체계화와 온-라인화에 따라 자동화된 설비진단 방법이 요구되어지고 있다. 이에 따라 기계설비에 각종 센서를 부착하여 실시간으로 수집된 출력신호를 이용하여 기계설비를 온-라인으로 감시하는 여러가지 기법들이 제시되고 있다. 본 연구에서는 진동센서로부터의 신호를 radial 함수에 근거한 다단계 뉴럴 네트워크(Neural Network)로 모형화하여 기계설비 상태를 감시하는 방법을 제시한다. 또한 다단계 모델링 분석을 통하여 신호를 예측하고 설비고장 원인을 분류하며, 다른 모형과의 비교를 통하여 효율성 평가와 최적 단계수를 결정하였다. 온라인 학습 알고리즘은 recursive least squares와 clustering 방법을 이용한다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.361-366
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• 2002

It has been reported that neural network with cyclic connections generates limit cycles. The dynamics of discrete time network with cyclic connections has been analyzed. But the dynamics of cyclic network in continuous time has not been known well due to its huge calculation complexity. In this paper, we study the dynamics of the continuous time network with cyclic connections and the effect of chaotic signal in the network for transitions between limit cycles.

• JOURNAL OF ELECTRICAL WORLD
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• no.8 s.200
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• pp.84-90
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• 1993

• Computational Structural Engineering
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• v.9 no.3
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• pp.29-33
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• 1996

• Computational Structural Engineering
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• v.9 no.3
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• pp.34-46
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• 1996

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.193-198
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• 2020

The various uses of the Convolutional Neural Network technology are accelerating the evolution of the computing area, but the opposite is causing serious hardware performance shortages. Neural network accelerators, next-generation memory device technologies, and high-bandwidth memory architectures were proposed as countermeasures, but they are difficult to actively introduce due to the problems of versatility, technological maturity, and high cost, respectively. This study proposes DRAM-based main memory technology that enables read operations to be completed without waiting until the end of the refresh operation using pre-stored XOR bit values, even when the refresh operation is performed in the main memory. The results showed that the proposed technique improved performance by 5.8%, saved energy by 1.2%, and improved EDP by 10.6%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.