• Korean Journal of Optics and Photonics
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• v.4 no.3
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• pp.294-300
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• 1993

Monolithic NOR and INVERTER active optical logic devices inte- grated with surface-emitting microlasers, heterojunction photo- transistors(HPT) in parallel and resistors in series are characterized. The differential quantum efficiency of the typical AlGaAs superlattice microlaser integrated in the active optical logic devices is 15%. Current gain of the HPT is 57, when emitter-collector voltage and input optical power are 4 V and $50{\mu}W$, respectively. $57{\mu}W$ of output power from the active optical logic device decreases to zero when $47{\mu}W$ of input optical power is incident on the HPT part of the active logic device.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.200-204
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• 2006

본 연구에서는 새로 고안된 NOT-AND 논리에 의한 방전 논리 gate PDP의 입력 DC 방전특성에 대해 고찰하고 동작특성을 해석하였다. 새로 고안된 방전 AND gate는 방전 경로에 따른 전극사이의 전위차의 변화로 AND 출력을 유도한다. 이러한 방전 논리 소자를 가지는 PDP에서는 직류방전이 논리게이트의 역할을 한다. 실험결과 이 DC 입력방전을 위해 priming 방전을 인가한 경우가 인가하지 않은 경우에 비해 방전지연시간이 1/3로 단축되며 방전개시전압은 1/2로 감소하였다. 또한 이 priming 방전은 방전종료후 $30{\mu}s$ 정도까지 영향을 미친다. 그리고 이 직류방전의 시간적, 위치적 방전특성을 측정한 결과, 방전에 따른 시간적 거리의 변화는 상당한 영향을 미치나 인접 전극들의 위치적인 영향은 거의 미미하다는 결론을 얻었다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• 한국정보교육학회:학술대회논문집
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• 2006.08a
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• pp.109-115
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• 2006

오늘날 IT의 급속한 진보는 사회적, 경제적 변화를 가져왔다. 그리고 많은 나라들이 정보화시대에 선두를 차지하려 노력하고 있다. 이에 미래의 IT산업을 선도할 인재들의 첫 출발점이라고 할 수 있는 초등학교에서의 정보영재교육의 필요성이 더욱 중요시되고 있으며, 현대 디지털 사회 전 분야에 걸쳐 없어서는 안 될 필수적인 요소로 사용되고 있는 디지털 시스템의 동작 원리를 이해하는 것이 요구되고 있다. 이에 디지털 시스템의 동작 원리를 이해하는 데 기초가 되는 디지털 논리 회로에 대한 내용을 초등학교 아동들이 쉽고 흥미롭게 이해할 수 있는 교육방법을 개발하여 실생활에서 필요한 디지털 시스템을 창의적으로 설계하고, 이를 통한 문제해결능력을 향상하고자 한다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.9-15
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• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.190-192
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• 2007

PICOM (Piece of Information for COMmunication)은 논리노드 간에 교환되는 정보를 기술하기 위하여 정의되어 있다. 변전소의 기능은 여러 논리노드로 분할되어 서로 상호작용하며 동작한다. 변전소 자동화 시스템 검사는 단일 IED만의 기능 시험이 아니며 IED들간에 메시지를 교환을 통하여 변전소 기능을 정의된 성능을 만족하며 수행하는지 검사하는 것이다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.1-6
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• 1975

본 논문은 Platen동작제어에 의한 한글델레타이프외 세가지 제어논리회로를 설계검토하였다. 일반적인 논리회로 구성방법에 의한 설계결과, 상태, 상태변이함수 그리고 출력함수외 순서로 설계한 Pulse mode의 제어회로가 가장 간단하였다. 이때 필요한 기억소자는 D Flip-Flop 2회 뿐이었다.

• Journal of IKEEE
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• v.20 no.2
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• pp.184-187
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• 2016

In this paper, we propose the sensor and the signal duplicator for the automatic building control. Developed duplicator realizes the sensor data collection apparatus and mimics the measured data and, thus, reduces the construction cost by using logical communication layer. Furthermore, the system supports the open protocols and can be associated with HMI(Human Machine Interface) used on the market. Developed duplicator is proved to be functional within the real environment. Measurement error rate, operating temperature, and operating humidity show very good results by the certified testing apparatus and organization.