• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.137-148
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• 1997

Diagnostic problem solving is a major application area of knowledge-based systems research. However, most of the current approaches, both heuristic and model-based, are designed to identify single faults, and do not generalize easily to multiple fault diagnosis without exhibiting exponential behavior in the amount of computation required. In this paper, we employ a decomposition approach based on system configuration to generate an efficient algorithm for multiple fault diagnosis. The basic idea of the algorithm is to reduce the inherent combinatorial explosion that occurs in generating multiple faults by partitioning the circuit into groups that correspond to output measurement points. Rules are multiple faults by partitioning the circuit into groups that correspond to output measurement points. rules are developed for combining candidates from individual groups, and forming consistent sets of minimal candidates.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• The KIPS Transactions:PartD
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• v.10D no.4
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• pp.671-678
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• 2003

A digital video is usually very long temporally. requiring large storage capacity. Therefore, users want to watch pre-summarized video before they watch a large long video. Especially in the field of sports video, they want to watch a highlight video. Consequently, highlight video is used that the viewers decide whether it is valuable for them to watch the video or not. This paper proposes how to create soccer video highlight using the structural features of the caption such as temporal and spatial features. Caption frame intervals and caption key frames are extracted by using those structural features. And then, highlight video is created by using scene relocation, logical indexing and highlight creation rule. Finally. retrieval and browsing of highlight and video segment is performed by selection of item on browser.

• Journal of KIISE:Software and Applications
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• v.28 no.9
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• pp.662-668
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• 2001

Since the problem of disproving a tautology is as hard as the problem of proving it, no polynomial time algorithm for falsification(or testing invalidity) is feasible. Previous algorithms are mostly based on either divide-and-conquer or graph representation. Most of them demonstrated satisfactory results on a variety of input under certain constraints. However, they have experienced difficulties dealing with big input. We propose a new falsification algorithm using a Merge Rule to produce a counterexample by constructing a minterm which is not satisfied by an input expression in DNF(Disjunctive Normal Form). We also show that the algorithm is consistent and sound. The algorithm is based on a greedy method which would seek to maximize the number or terms falsified by the assignment made at each step of the falsification process. Empirical results show practical performance on big input to falsify randomized nontautological problem instances, consuming O(nm$^2$) time, where n is the number of variables and m is number of terms.

• Journal of the Korean School Mathematics Society
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• v.15 no.3
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• pp.565-584
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• 2012

This study investigates how the GSP helps gifted and talented students understand geometric principles and concepts during the inquiry process in the generalization of the internal triangle, and how the students logically proceeded to visualize the content during the process of generalization. Four mathematically gifted students were chosen for the study. They investigated the pattern between the area of the original triangle and the area of the internal triangle with the ratio of each sides on m:n respectively. Digital audio, video and written data were collected and analyzed. From the analysis the researcher found four results. First, the visualization used the GSP helps the students to understand the geometric principles and concepts intuitively. Second, the GSP helps the students to develop their inductive reasoning skills by proving the various cases. Third, the lessons used GSP increases interest in apathetic students and improves their mathematical communication and self-efficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.521-528
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• 2017

Research on AI is essential to build a system with collective intelligence that allows a large number of UAVs to maintain their flight while carrying out various missions. A typical approach of AI includes 'top-down' approach, which is a rule-based logic reasoning method including expert system, and 'bottom-up approach' in which overall behavior is determined through partial interaction between simple objects such as artificial neural network and Flocking Algorithm. In the same study as the existing Flocking Algorithm, individuals can not perform individual tasks. In addition, studies such as UAV formation flight can not flexibly cope with problems caused by partial flight defects. In this paper, we propose organic integration between top - down approach and bottom - up approach through multi - agent system, and suggest a flight flight algorithm which can perform flexible mission through it.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.352-362
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• 2010

The simultaneous operation of multiple UAV's makes it possible to enhance the mission accomplishment efficiency. In order to achieve this, easily scalable control algorithms are required, and swarm intelligence having such characteristics as flexibility, robustness, decentralized control, and self-organization based on behavioral model comes into the spotlight as a practical substitute. Recently, evolutionary robotics is applied to the control of UAV's to overcome the weakness of difficulties in the logical design of behavioral rules. In this paper, a neural network controller evolved by evolutionary robotics is applied to the control of multiple UAV's which have the mission of searching limited area. Several numerical demonstrations show the proposed algorithm has superior results to those of behavior based neural network controller which is designed by intuition.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.65-76
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• 2005

A digital video is a very long data that requires large-capacity storage space. As such, prior to watching a long original video, video watchers want to watch a summarized version of the video. In the field of sports, in particular, highlights videos are frequently watched. In short, a highlights video allows a video watcher to determine whether the highlights video is well worth watching. This paper proposes a scheme for creating soccer video highlights using the structural features of captions in terms of time and space. Such structural features are used to extract caption frame intervals and caption keyframes. A highlights video is created through resetting shots for caption keyframes, by means of logical indexing, and through the use of the rule for creating highlights. Finally, highlights videos and video segments can be searched and browsed in a way that allows the video watcher to select his/her desired items from the browser.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.