• Korean Journal of Logic
• /
• v.22 no.1
• /
• pp.25-42
• /
• 2019

This paper deals with Kripke-style semantics, which will be called set-theoretic Kripke-style semantics, for weakly associative substructural fuzzy logics. We first recall three weakly associative substructural fuzzy logic systems and then introduce their corresponding Kripke-style semantics. Next, we provide set-theoretic completeness results for them.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.1
• /
• pp.147-156
• /
• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1985.04a
• /
• pp.6-8
• /
• 1985

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.2
• /
• pp.113-118
• /
• 2005

This paper shows a satellite battery cell voltage monitor system to make differential voltage measurements when one or both measurement points are beyond voltage range allowed by a conventional differential amplifier. This system is particularly useful for monitoring the individual cell voltage of series-connected cells that constitute a rechargeable satellite battery in which some cell voltages must be measured in the presence of high common mode voltage.

• Proceedings of the KSRS Conference
• /
• 2007.03a
• /
• pp.109-112
• /
• 2007

본 논문에서는 대축척 수치지도와 Quickbird 위성영상의 자동 보정을 영상공간에서 수행한다. 알고리즘은 보정변환식의 초기 계수값 결정과 정확한 변환계수 결정과정으로 나뉜다. 초기 계수값 결정은 보정변환식의 상수항을 결정하는 것으로 수치지형도의 지면개체와 영상에서 추출된 에지의 논리곱 연산을 적용하여 최적값을 추정하는 방식을 용한다. 보정 다항식의 정확한 변환계수를 결정하기 위하여 수치지형도의 지면 선형개체 점데이터와 영상의 에지개체 점데이터간 ICP 조정을 수행하였다. 제안된 방법의 정확도를 평가한 결과， 영상공간에서 1.72화소의 RMSE를 나타내었다.

• Journal of IKEEE
• /
• v.12 no.4
• /
• pp.211-216
• /
• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Korean Journal of Logic
• /
• v.19 no.3
• /
• pp.437-461
• /
• 2016

This paper investigates weakening-free fuzzy logics with three weak forms of associativity (of multiplicative conjunction &). First, the wta-uninorm (based) logic $WA_tMUL$ and its two axiomatic extensions are introduced as weakening-free weakly associative fuzzy logics. The algebraic structures corresponding to the systems are then defined, and algebraic completeness results for them are provided. Next, standard completeness is established for $WA_tMUL$ and the two axiomatic extensions with an additional axiom using construction in the style of Jenei-Montagna.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.6
• /
• pp.9-15
• /
• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• Journal of IKEEE
• /
• v.9 no.1 s.16
• /
• pp.1-6
• /
• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.11
• /
• pp.4597-4603
• /
• 2010

A factorization is a very important part of multi-level logic synthesis. The number of literals in a factored form is an estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube nonkernel Boolean pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over previous other factorization methods.