• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.651-654
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• 2008

In finite field operations based on $GF(2^m)$, additions and subtractions are easily implemented. On the other hand, multiplications and divisions require mathematical elaboration of complex equations. There are two dominant way of approaching the solutions of finite filed operations, normal basis approach and polynomial basis approach, each of which has both benefits and weakness respectively. In this study, we adopted the mathematically feasible polynomial basis approach and suggest the optimization techniques of finite field operations based of mathematical principles.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.169-170
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• 2018

이진체 상의 타원곡선 B-233을 지원하는 타원곡선 암호 프로세서를 32-비트 워드기반 몽고메리 곱셈기를 이용하여 설계하였다. 스칼라 곱셈을 위해 수정된 몽고메리 래더 (Modified montgomery ladder) 알고리즘을 적용하여 단순 전력분석에 내성을 갖도록 하였으며, Lopez-Dahab 투영 좌표계와 페르마의 소정리(Fermat's little theorem)를 적용하여 하드웨어 자원 소모가 큰 나눗셈과 역원 연산을 제거하여 저면적으로 설계하였다. 설계된 ECC 프로세서는 Xilinx ISim을 이용하여 기능검증을 하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 100 MHz의 동작 주파수에서 9,614 GEs와 4 Kbit RAM으로 구현되었으며, 최대 동작 주파수는 125 MHz로 예측되었다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• The Mathematical Education
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• v.58 no.2
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• pp.319-335
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• 2019

In this paper, we examine the effectiveness of calculation according to automation, which is one of Computational Thinking, by coding the conceptual process into Python language, focusing on the concept of divisibility in elementary school textbooks. The educational implications of these considerations are as follows. First, it is possible to make a field of learning that can revise the new mathematical concept through the opportunity to reinterpret the Conceptual Thinking learned in school mathematics from the perspective of Computational Thinking. Second, from the analysis of college students, it can be seen that many students do not have mathematical concepts in terms of efficiency of computation related to the divisibility. This phenomenon is a characteristic of the mathematics curriculum that emphasizes concepts. Therefore, it is necessary to study new mathematical concepts when considering the aspect of utilization. Third, all algorithms related to the concept of divisibility covered in elementary mathematics textbooks can be found to contain the notion of iteration in terms of automation, but little recursive activity can be found. Considering that recursive thinking is frequently used with repetitive thinking in terms of automation (in Computational Thinking), it is necessary to consider low level recursive activities at elementary school. Finally, it is necessary to think about mathematical Conceptual Thinking from the point of view of Computational Thinking, and conversely, to extract mathematical concepts from computer science's Computational Thinking.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.119-122
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• 2004

G.723.1은 저 전송률 환경에서 고 음질을 제공하여 주고 있으나 CELP형 부호화기가 갖는 합성에 의한 분석(Analysis by Synthesis)방식의 구조로 인해 많은 처리 시간과 계산량을 요구하게 된다. 본 논문에서는 G.723.1에 대해 NAMDF함수를 적용하여 델타 피치 검색과정의 계산량을 줄여 부호화기의 전체 계산량을 감소시키는 방법을 제안하였다. 기존의 피치 검출 알고리즘에서 피치 검출을 위해 사용하고 있는 자기상관함수는 곱셈 연산에서 발생하는 bit의 dynamic range가 커서 나눗셈 연산에서도 과도한 연산량을 필요로 한다. 따라서, 이러한 계산량의 감소를 위해 기존의 자기상관함수 대신 계산량을 감소하기 위하여 NAMDF 방법을 적용하였고 추가된 skipping 기법을 사용하였다. 계산량 감소율 측면에서는 약 $64\%$의 감소율을 보였고 기존의 방법과 제안한 방법간의 피치 pitch contour은 원음성의 피치 contour와 유사하였고, 음질 평가에서도 기존의 G.723.1 부호화기 합성음과 유사한 길과를 얻을 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.112-117
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• 2004

In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}＋1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.

• Journal of the Korean School Mathematics Society
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• v.11 no.2
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• pp.285-298
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• 2008

According to the 7th curriculum, irrational numbers should be introduced using infinite decimals in 9th grade. To do so, the relation between rational numbers and decimals should be explained in 8th grade. Preceding studies remarked that middle school students could understand the relation between rational numbers and decimals through the division appropriately. From the point of view with the arithmetic handling activity, I analyzed that the integers and terminating decimals was explained as decimals with repeating 0s or 9s. And, I reviewed the equivalent relations between irrational numbers and non-repeating decimals, rational numbers and repeating decimals. Furthermore, I suggested an alternative method of introducing irrational numbers.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.292-295
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• 2003

블루투스 전송 기술은 2.4㎓ 의 ISM(Industrial Scientific Medicine)밴드에서 주파수 호핑 방식을 사용한다. 주파수 호핑율은 연결 상태에서 초당 1600회, 조회 또는 호출 상태에서 초당 3200회의 호핑을 한다. Hop 채널 선택은 블루투스 표준안에서 제시한 5개의 호핑 시퀸스 중 하나를 선택하고 호핑 주파수에 따라 이를 매핑 함으로써 이루어진다. 본 논문에서는 6개의 상태에 따라 다르게 실행되는 채널 계산을 효율적으로 제어하고 필요한 연산모듈의 수를 줄이기 위해 9비트 프로세서를 이용해 Hop 선택 모듈을 설계하고 구현한다. 설계된 모듈은 레지스터 파일, 마이크로프로그램 제어장치, 가산, 치환(permutation), Modulo 계산을 위한 3개의 연산장치로 구성된다. Hop 채널 계산 중 가장 클럭 소요가 큰 Modulo 연산은 SRT나눗셈 알고리즘을 사용하여 음수 값 계산 및 연산 속도 향상을 꾀하였다. 제시된 Hop 선택 모듈은 하드웨어 묘사언어인 VHDL로 설계하고 시뮬레이션 및 테스트는 Xilinx FPGA를 이용해 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.1009-1018
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• 2003

A new fading channel estimation technique is proposed for an OFDM based modem In the ITS system. The algorithm is based on the transfer function extraction of the channel using the pilot signals and compensated the channel preceding the equalization. The newly derived algorithm is division-free arithmetic operations allows the faster circuit operation and the smaller circuit size. Proposed techniques compensate firstly the distortion which is generated at fading channels and secondly eliminate inter-symbol interference. All algorithms are suitability estimated and improved for a system implementation using digital circuits. As the results, the circuit size is reduced by 20% of the conventional design and achieved about 10% performance improvement at low SNR under 10dB in case of ITS system adapted 16-QAM mode.