• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.400-403
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• 2010

본 논문에서는 디지털 카메라의 자동초점 속도를 향상시키는 새로운 기법을 제안한다. 제안된 방식은 위상차 검출 방식에서 사용되는 추가적인 자동초점 모듈을 장착하지 않으면서도 빠르게 초점이 맞는 위치의 거리와 방향을 계산할 수 있는데, 이는 이중 분할 조리개를 이용하여 위상차가 발생하도록 하고, 컬러 필터를 이용하여 분리함으로써 소프트웨어 영상 처리만으로 위상차를 측정하여 정확한 초점 위치를 찾을 수 있기 때문이다. 이중 분할 조리개에 의해서 발생한 컬러 영상 채널 간의 상이한 정도를 측정하기 위하여 초점이 맞는 정도를 수치화 할 수 있는 유사도 측정 기준을 제시하는데, 이 기준으로 측정된 유사도를 비교함으로써 불일치 정도를 추출하며 정확한 초점을 잡기 위한 거리와 방향을 계산한다. 실험에서는 상용 디지털 카메라를 개조한 프로토 타입에서 취득한 영상을 사용하여 제안한 방식의 유효성을 검증하였다.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.415-417
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• 2003

TOA(Time of Arrival) 및 TDOA(Time Difference of Arrival)경우 무선국의 시간동기화를 위해서 고도의 기술을 요구하고 있으며, 시간동기오차에 따른 위치검지의 정밀도가 낮아지는 문제가 있어 이를 극복하기 위하여 위상차를 이용한 새로운 열차검지기법의 제안에 따른 구현을 위하여 무선장치 설계에 대하여 기술하고자 한다. 본 시스템은 전파의 전달 속도($\lambda$)를 응용하여 기준 주파수인 1.5MHz를 송신 시스템과 수신 시스템의 기준 주파수와 비교하여 그 위상의 차이를 비교하여 지연된 시간을 구한 후 이를 거리로 환산하는 시스템으로서 무선장치와 S/W로 구분하여 구현 설계하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1858-1863
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• 2000

본 논문에서는 SPD(Sampling Phase Detector)를 이용한 위상고정 방법의 무선 CATV용 위상 고정 유전체 공진 발진기(PLDRO)를 설계·제작하였다. 이 발진기는 하이브리드 형태인 12.875 GHz의 VCDRO(Voltage Controlled Dielectric Resonator Oscillator)와 완충 증폭기, 방향성 결합기, 주파수 체배기, 샘플링 위상 검출기, 루프 필터, 기준 주파수 발진기, VHF 증폭기로 구성되어 있다. 위상 고정 유전체 공진 발진기의 발진출력은 25.75 GHz에서 1.17 dBm, 기본주파수 억압 -27.83 dBc로 안정된 위상고정 상태를 나타내었다. 이때의 위상잡음은 -101.7 dBc/Hz @ 100KHz로 측정되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.149-152
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• 2005

본 논문은 디지털 마이크로파 다수 반송파 시스템에 적용되는 고안정 국부발진기의 위상잡음에 대해서 분석하였다. 위상잡음의 영향을 분석하기 위해 Lorantizan모델을 사용하여 위상잡음 분산값을 구하였으며, 기저대역 I, Q채널에서 BER과의 특성을 모의실험 하였다. 시스템에 미치는 영향을 알아보기 위해서 BER특성을 분석한 결과, 위상잡음에 따라 영향을 많이 받으며, 특히 고차원 변조방식을 가질수록 위상잡음에 더 영향을 많이 받음을 확인하였다. 모의실험결과 BER을 10$^{-5}$을 기준으로 했을 경우, QPSK 변조방식은 분산값에 따라서 대략 4dB, 16-QAM 변조방식은 대략 9dB 정도의 성능차이를 나타내었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.612-617
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• 2012

Two phase control (PC) schemes using limited feedback are proposed for multiple-input single-output (MISO) systems. One PC scheme cophases channel gains with respect to the first transmit antenna channel gain, and the other PC scheme cophases channel gains by positioning all the channel gains into a fixed sector. We analyze the combined channel gain for both PC schemes, and find that the PC scheme that cophases with respect to the first transmit antenna channel gain provides 1.2 dB power gain over an orthogonal space-time block code (OSTBC) when the number of transmit antennas is four and the number of feedback bits is three.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1199-1206
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• 2018

The hybrid phase shifting device is consist of general phase shifter in sub-array and the true time delay inter sub-array. This configuration for phased shifting can efficiently improve the beam squint according to frequencies. However, when an appropriate array configuration is not selected, a gain variation of main lobe for a phased array antenna is occurred. In order to solve these problems, a simplified formula for constructing efficient array based on the system design requirements, such as the fractional bandwidth, the maximum beam steering angle, and limit criterion of the gain variation, was presented.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1805-1810
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• 2014

The phase noise spectrum distribution for remote controller using the BPSK mode and low data rate of 50 kbps was designed and proposed in this paper. In case of applying the BPSK that transmission performance is superior to FSK method, the performance degradations due to phase noise are generated. To minimize the phase noise effect, it is important to dispatch the digital signal in channel environment with required phase noise characteristics. To provide the terminal design technique and the proper channel environment with required phase noise characteristics, the phase noise spectrum distribution was designed for required phase noise characteristics. By analyzing the phase noise effects for damping factor and noise bandwidth of the carrier recovery circuit, the phase noise spectrum design that consider the damping factor and noise bandwidth was performed. Based on the IESS-308 standards, also, the phase noise effects was analyzed. The phase noise spectrum design techniques and phase noise spectrum that is suitable to remote controller were proposed.

• Journal of Navigation and Port Research
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• v.36 no.6
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• pp.475-480
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• 2012

In order to establish eLoran (enhanced Long Range Navigation) system, it needs the advancement of receiver, transmitter, data channel addition for Loran information, differential Loran sites for compensating Loran-c signal and ASFs (Additional Secondary Factors) database, etc. In addition, the precise synchronization of transmitting station to the UTC (Coordinated Universal Time) is essential if Loran delivers the high absolute accuracy of navigation demanded for maritime harbor entrance. For better timing synchronization to the UTC among transmitting stations, it is necessary to measure and monitor the transmission delay of the station, and the correction information of the transmitting station should be provided to the user's receivers. In this paper we presented the measurement method of absolute delay of Pohang Loran transmitting station and developed a time delay measurement system and a phase monitoring system for Loran station. We achieved -2.23 us as a result of the absolute phase delay of Pohang station and the drift of Loran pulse of the station was measured about 0.3 us for a month period. Therefore it is necessary to measure the delay offset of transmitting station and to compensate the drift of the Loran signal for the high accuracy application of PNT (Positioning, Navigation and Timing).