• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.1
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• pp.142-148
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• 2014

The mirror which is considered in designing a MFD is off-axis primary one and its dimension is wide 556mm height 345mm. The MFD(Mirror Fixation Device) load specification is generated for the high resolution mirror. The optical WFEs for unit loads are calculated from mirror sensitivity analysis and they are compared with allocated allowable optical WFE. The parasite load for the MFD is calculated from their comparison. The MFD compliant with the parasite load is designed.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of Conservation Science
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• v.16 s.16
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• pp.77-88
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• 2004

This study evaluates the occurrences, phyfical weathering and biological deterioration on rock properties during the dissection process an object of stone pagoda in the Mireuksaji temple site. For restoration and conservation, all kinds of rock properties are carried out detailed scientific investigation and diagnosis. Constituting rocks of the pagoda composed mainly of equi-granular medium grained biotite that rock properties presumed to be use about 3,000 materials. Main external properties of the pagoda are total 446 materials, and the rock properties under the concentration load on the each floors occurred with overlapping fracture, weathering and deteriorations. The 84 materials show highly degraded about $18.8\%$ among the external properties. Representative physicochemical deteriorations are fracture, loss, break, exfoliation, degradation, grain shaped dissolution, relief surface, discoloration and hydroxide precipitates, in this study, the deterioration state of each properties give a precisely description and analysis. Coverage of lichen and algae on the rock surface represented about $85\%$. As the some properties, biological contaminants withered up when spray rock surface with diluted cleaning chemicals. Results of the study are utilized an application for restoration system and detailed investigation during the dissection process of stone cultural properties.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.