• The Journal of Society for e-Business Studies
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• v.25 no.2
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• pp.109-126
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• 2020

This study attempts to find out the characteristics of digital currency and currency transformation through the analytical descriptions of the literature. In the early days of the emergence of new currency, market-oriented autonomous monetary adjustment was made along with various attempts by the private sector, and then government-centered central currency management and coordination were made for the national monopoly of profits and power. Digital currency can be seen as the emergence of a new form of money that will bring about paradigm changes. CBDC can be divided into direct and indirect types. CBDC is expected to require a strategic approach by the government or firm as it will bring about changes in the ecosystem of related industries. Libra is a stablecoin designed to minimize price fluctuations, and if it succeeds in commercializing it, it is expected to bring about revolutionary changes in the financial industry around the world.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.1-11
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• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of Korea Spatial Information System Society
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• v.10 no.2
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• pp.13-24
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• 2008

A next generation video based car navigation is researched to supplement the drawbacks of existed 2D based navigation and to provide the various services for safety driving. The components of this navigation system could be a load object database, identification module for load lines, and crossroad identification module, etc. In this paper, we proposed the traffic lights and road sign recognition method which can be effectively exploited for crossroad recognition in video-based car navigation systems. The method uses object color information and other spatial features in the video image. The results show average 90% recognition rate from 30m to 60m distance for traffic lights and 97% at 40-90m distance for load sign. The algorithm also achieves 46msec/frame processing time which also indicates the appropriateness of the algorithm in real-time processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.35-40
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• 2010

In this paper, we propose a hardware resource sharable camera control processor (CCP) for low-cost and low-power camera cell phones. The main idea behind the proposed architecture is that adds direct access paths in the CCP to share its hardware resources so that the baseband processor expands its capabilities and boosts its performance by utilizing CCF's hardware resources. In addition, we applied a module grain dock-gating method to reduce power dissipation. Hence, the CCP can realize low-power and low-cost camera cell phones with greater hardware efficiency. This chip was fabricated in a 0.18um CMOS process with an active area of $3.8mm\;{\times}\;3.8mm$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.11
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• pp.955-962
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• 2016

In recent years, there have been emerging needs for standardized software-based motion application development for better scalability and support for multiple operation modes for small quantity batch production. Although a software-based motion system provides a basis for constructing multiple operation modes on a machine, it is not easy to construct such systems without tools for defining multiple motion operation modes and standardized mode-change protocols. This paper proposes a motion recipe concept to overcome this problem; the concept includes the authoring of multiple motion operation modes using the PLCopen-compliant motion function blocks and communication protocols to trigger operation mode changes from an external interface. The motion recipe was implemented by extending an IEC 61131-3 compliant IDE called Beremiz, and the correctness of the motion recipe-based application behavior was verified on a real testbed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.1
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• pp.20-27
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• 2020

In general, a nonlinear system is linearized in the form of a multiplication of the 1st and 2nd order system. This paper reports a design method of a weighting matrix and control law of LQ control to move the double poles that have a Jordan block to a pair of complex conjugate poles. This method has the advantages of pole placement and the guarantee of stability, but this method cannot position the poles correctly, and the matrix is chosen using a trial and error method. Therefore, a relation function (𝜌, 𝜃) between the poles and the matrix was derived under the condition that the poles are the roots of the characteristic equation of the Hamiltonian system. In addition, the Pole's Moving-range was obtained under the condition that the state weighting matrix becomes a positive semi-definite matrix. This paper presents examples of how the matrix and control law is calculated.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1069-1079
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• 2005

Though there have been many methods to detect features in spatial domain, in the case of a compressed image it has to be decoded, processed and encoded again. Alternatively, we can manipulate a compressed image directly in the Discrete Cosine Transform (DCT) domain that has been used for compressing videos or images in the standards like MPEG and JPEG. In our previous work we proposed a model-based discontinuity evaluation technique in the DCT domain that had problems in the rotated or non-ideal discontinuities. In this paper, we propose a fuzzy filtering technique that consists of height fuzzification, direction fuzzification, and forty filtering of discontinuities. The enhancement achieved by the fuzzy tittering includes the linking, thinning, and smoothing of discontinuities in the DCT domain. Although the detected discontinuities are rough in a low-resolution image for the size (8${\times}$8 pixels) of the DCT block, experimental results show that this technique is fast and stable to enhance the qualify of discontinuities.