• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.224-226
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• 2010

컴퓨터 생성 홀로그램(computer-generated hologram, CGH) 기법은 광학 신호들을 근사화한 후 PC에서 수학적인 연산으로 디지털 홀로그램을 생성하는 기술이다. 본 논문에서는 CGH 기법을 하드웨어로 구현할 경우 완벽한 병렬처리와 파이프라이닝이 가능하도록 연산식을 최적화하는 방법을 제안한다. 제안한 방법은 홀로그램의 이전 좌표에서 계산된 값에 일정한 값을 더하여 홀로그램을 생성하는 반복가산 기법의 일반항을 분석하여 하드웨어에 최적화된 수식으로 변형하는 것이다. 최적화된 수식의 경우 현재 좌표의 홀로그램을 계산하기 위해 이전 좌표에서 연산되었던 결과값을 기다렸다 이용하지 않기 때문에 실시간 디지털 홀로그래피를 위한 전용 하드웨어의 설계에 적합할 것이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.320-323
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• 2010

This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.58-68
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• 2024

Approximate computing is a promising approach that optimizes hardware components while tolerating some degree of accuracy loss. In particular, approximate multiplication is widely used as a key operation in computing systems that demand both high performance and low power consumption. Among various techniques, the approximate 4-2 compressor has gained attention for its ability to significantly enhance the performance and efficiency of approximate multiplier through benefits such as low power consumption, improved processing speed, and circuit simplification. A multiplier that computes the product of two n-bit numbers typically consists of three stages: partial product generation, partial product reduction, and adder. By using an approximate 4-2 compressor, the partial product reduction stage can be simplified, and errors introduced by approximation can be compensated for using error correction modules. Additionally, constant correction techniques can be employed to further reduce errors. This paper explores the characteristics of approximate 4-2 compressors and compares various models. Based on this analysis, we evaluate different error metrics and synthesis results for an 8×8 approximate multiplier. Furthermore, we conduct a comparative analysis by applying the multiplier to image processing tasks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1736-1738
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• 2016

In modern digital communication systems adapting high-order modulation and high performance channel code, log-likelihood ratios involving the repeated calculations of the logarithm of sum of exponential functions are necessary for demodulation and decoding. In this paper, the approximation methods called Min and MinC are applied to demodulation and decoding together and their complexity and joint performance are analyzed.

• Computational Structural Engineering
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• v.10 no.2
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• pp.273-281
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• 1997

In the structural analysis, artificial neural networks as a parallel computational model that is similar to the human brain and can self-organize complex nonlinear relationships without making assumptions is introduced. The purpose of this paper is to develop the Neural Network for Approximate Structural Analysis(NNASA) to predict the behaviour of the stub-girder system. As an initial stage, the paper presents the development of the prototype of NNASA based on the problem related to the deflection of a simple beam, and shows the verification of this model by two examples.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.321-326
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• 1998

본 논문에서는 정밀 제어와 온-라인 제어를 위하여 유전 알고리즘을 이용한 퍼지-신경망 제어기를 제안하였다. 제안된 제어기의 설계방법은 다음과 같은 3단계의 동조과정으로 구성한다. 1) 퍼지 제어기의 비퍼지화 연산을 신경망을 이용하여 함수근사화 시킨 후, 퍼지-신경망 제어기를 구성한다. 2) 플랜트에 적합한 퍼지 소속함수의 형태를 얻기 위해 유전 알고리즘을 이용하여 근사화된 퍼지 소속함수를 찾는다. 3) 근사화된 초기 퍼지 소속함수를 퍼지-신경망 제어기에 의해 적응학습으로 최적의 퍼지 소속함수를 얻고, 또한 플랜트의 파라미터 변동이나 외부환경의 변화에 대해 적응할 수 있도록 최적의 퍼지 소속함수를 추정한다. 제안된 제어기의 성능을 평가하기 위하여 DC 서보모터의 속도제어에 적용하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.322-328
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• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.191-199
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• 2005

Space-time turbo codes have been studied extensively as a powerful and bandwidth efficient error correction code over the wireless communication environment. In this paper, the efficient algorithm for decoding space-time turbo codes is proposed. The proposed method reduces the computational complexity by approximating a prior information for a iterative decoder. The performance of space-time turbo codes is also analyzed by using the fixed point implementation and the efficient method for approximating the Log-MAP algorithm is proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Journal of Advanced Navigation Technology
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• v.3 no.2
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• pp.139-146
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• 1999

A flight simulator is composed of engine, navigation systems and instrument modules. However, two problems exist here. First, the coordinate of each independent module is not same. To solve this problem, we design a method that mutual coordinates are capable of transformation each other. Second, the distance and bearing between two points on the earth are computed in a sphere shape using the spherical trigonometry. However, the computing time is very severe. In this paper, we project the sphere into the planar to reduce the computing time. An experimental result shows that the performance of the proposed method is excellent to both distance and bearing calculations in close region. Also, the computing time is reduced from $4.95{\times}10^{-4}$ seconds to $1.648{\times}10^{-4}$ seconds.