• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.

• Journal of the Korean Association of Geographic Information Studies
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• v.26 no.3
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• pp.12-36
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• 2023

Graph databases, which store different types of data and their relationships modeled as a graph, can be effective in managing and analyzing real estate spatial data linked by complex relationships. However, they are not widely used due to the limited spatial functionalities of graph databases. In this study, we propose a uniform grid-based real estate spatial data management approach using a graph database to respond to various real estate-related spatial questions. By analyzing the real estate community to identify relevant data and utilizing national point numbers as unit grids, we construct a graph schema that linking diverse real estate data, and create a test database. After building a test database, we tested basic topological relationships and spatial functions using the Jackpine benchmark, and further conducted query tests based on various scenarios to verify the appropriateness of the proposed method. The results show that the proposed method successfully executed 25 out of 29 spatial topological relationships and spatial functions, and achieved about 97% accuracy for the 25 functions and 15 scenarios. The significance of this study lies in proposing an efficient data integration method that can respond to real estate-related spatial questions, considering the limited spatial operation capabilities of graph databases. However, there are limitations such as the creation of incorrect spatial topological relationships due to the use of grid-based indexes and inefficiency of queries due to list comparisons, which need to be improved in follow-up studies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1132-1138
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• 2002

This paper proposes a reducing power consumption of a scheduling algorithm for optimal selection of supply voltage. In scheduling of reduction power consumption, we determine the control steps of operations to be executed by exploiting the possibility of using variable voltage levels to reduce power consumption. In the optimal selection of supply voltage binding, we minimize the main factor of the power consumption of the switching activity on the registers using a graph coloring technique. From a set of experiments using high-level benchmark examples, we show that the proposed algorithm prefer to use optimal selection supply voltages rather than uniformed single voltage is effective in reducing power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• The Korean Journal of Applied Statistics
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• v.37 no.3
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• pp.355-380
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• 2024

In this paper, we compare the performance of graph-based deep learning models using OECD test guideline (TG) data. OECD TG are a unique tool for assessing the potential effects of chemicals on health and environment. but many guidelines include animal testing. Animal testing is time-consuming and expensive, and has ethical issues, so methods to find or minimize alternatives are being studied. Deep learning is used in various fields using chemicals including toxicity prediciton, and research on graph-based models is particularly active. Our goal is to compare the performance of graph-based deep learning models on OECD TG data to find the best performance model on there. We collected the results of OECD TG from the website eChemportal.org operated by the OECD, and chemicals that were impossible or inappropriate to learn were removed through pre-processing. The toxicity prediction performance of five graph-based models was compared using the collected OECD TG data and MoleculeNet data, a benchmark dataset for predicting chemical properties.

• Journal of KIISE:Software and Applications
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• v.26 no.5
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• pp.692-701
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• 1999

수퍼스칼라(superscalar)나 VLIW 와 같은 명령어 수준 병렬화(ILP) 프로세서의 성능을 극대화하는 과감한 명령어 스케쥴링은 소프트웨어 파이프라이닝과같은 스케쥴링 과정을 거치면서 일반적인 복사 명령어 제거 기법으로 없앨 수 없는 서로 간섭하는 복사 명령을 많이 만들어내는데 루프 내부에 생성된 이러한 복사명령은 적절한 루프 펼침을 수행하여 간섭관계를 없앰으로서 제거할 수 있다. 본 논문에서는 이와 같이 루프 펼침이 수행된 루프 내부의 복사명령을 제거하는 기법으로 그래프 컬러링 상에 구현한 낙관적 융합기법을 제안한다. 그래프 컬러링에서의 융합기법은 간선의 개수가 많은 노드를 만들어 낼수 있으므로 채색성에 부정적인 영향을 주는 것으로 알려져 왔으나 본 기법에서는 융합되는 노드에 동시에 간섭하는 노드의 간선의 수가 줄어드는 긍정적인 영향을 최대한 이용하여 채색성을 높이고 융합된 노드에 대한 실제 버림(spill)이 일어나는 경우 유효 범위 분절(live range splitting)을 통하여 버림의 부담을 최대한 줄이도록 하였으며 이를 VLIW 스케쥴링 된 SPEC 정수벤치마크 루프내부의 복사 명령 제거에 적용한 결과 제거 가능한 복사 명령의 99%를 제거하면서도 버림명령은 다른 융합 기법과 비교하여 가장 적게 발생하는 우수한 결과를 얻을수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.