• Title/Summary/Keyword: 그래프신호처리

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The Unified Wireless Control System for the Vibration Control of Bridge (교량의 진동제어를 위한 통합 무선제어 시스템)

  • Heo, Gwang Hee;Kim, Chung Gil;Oh, Ju Won
    • Journal of the Korea institute for structural maintenance and inspection
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    • v.16 no.2
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    • pp.65-74
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    • 2012
  • This paper aimed at the development of a unified wireless control system in order to control various forms of vibration of bridges. This unified wireless control system unified all different systems each of which functioned for difference purpose such as measurement, analysis, judgement, and control of data acquired from the movement of structure. It was designed to control structures with feedback which was returned according to each different situation after analyzing various signals measured about the structure. In this system, every information in each step from measurement to control was wirelessly transmitted to its central system so that a manager was able to effectively monitor the whole process. Just for the case when any system control need to intervene occurred, a graph user interface was designed for better access. In order to evaluate its basic performance, an experiment was carried out to see how signal input and output were done by comparing its results with those of a wired system. On the basis of the experiment, a vibration control experiment was performed on a model of cable-stayed bridge to see if the unified wireless control system worked well in realtime. This was carried out under four conditions, and the graph and quantitative result under each condition were compared each other. All experiments proved that the unified wireless control system functioned as well as the wired one in terms of its basic performance and vibration control.

Rapid Analytical Method of Volatile- and Semivolatile Organic Compounds in Water and their Monitoring in Water Treatment Plants (물 시료 중 휘발성 및 반휘발성 유기물질들의 빠른 분석법 및 정수처리 단계별 모니터링)

  • Shin, Ho-Sang;Ahn, Hye-Sil
    • Analytical Science and Technology
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    • v.17 no.3
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    • pp.240-250
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    • 2004
  • A gas chromatography-mass spectrometric (GC-MS) assay method was developed for the rapid and sensitive determination of volatile- and semivolatile organic compounds in water. Two hundreds mL of water sample was extracted in a 250 mL separatory funnel with 1 ml of pentane at pH 6.5. Fluorobenzene and 1,2-dichlorobenzene-d4 as internal standards were added to water sample and the solution was mechanically shaken for 5 min and analyzed by GC-MS (selected ion monitoring) without more any concentration or purification steps. The peaks had good chromatographic properties and the extraction of these compounds from water also gave relatively high recoveries with small variations. The range of detection limits of the assay was 0.5-10 ng/L. Turnaround time for up to about 40 samples was one day. This method is simple, convenient, and can be learned easily by relatively inexperienced personnel. This method was used to analyze 15 volatile- and semivolatile organic compounds in water of a Lake, and raw and treated water from three Water Treatment Plants in Korea. As the analytical results, benzene, toluene, xylene, isopropylbenzene, 1,3,5-trimethylbenzene, 1,2,4-trimethylbenzene, naphthalene and 2,4,6-trichlorophenol were detected at concentrations of up to 0.4, 1.9, 1.3, 0.2, 1.8, 13.0, 1.7 and $1.1{\mu}g/L$, respectively. But chlorobenzene, trichloroethylene, tetrachloroethylene, ethylbenzene, n-butylbenzene and dibromochloropropane levels during that period were not significant. The removal effect of the compounds in three Water Treatment Plants was calculated. The compounds studied were generally removed during conventional water treatment, especially during the active carbon filtration.

A Multiprocessor Scheduling Methodology for DSP Applications.

  • Hong, Chun-Pyo;Yang, Jin-Mo
    • Journal of Korea Society of Industrial Information Systems
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    • v.6 no.2
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    • pp.38-46
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    • 2001
  • This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

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Design of MSB-First Digit-Serial Multiplier for Finite Fields GF(2″) (유한 필드 $GF(2^m)$상에서의 MSB 우선 디지트 시리얼 곱셈기 설계)

  • 김창훈;한상덕;홍춘표
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.625-631
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    • 2002
  • This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

우리나라의 갈릴레오 탐색구조 지상시스템 개발 참여 방안

  • Ju, In-Won;Lee, Sang-Uk;Kim, Jae-Hun;Seo, Sang-Hyeon;Han, Dong-Su;Im, Jong-Geun
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.608-611
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    • 2006
  • COSPAS-SARSAT 시스템은 위성체와 지상 설비를 이용하여 항공기 또는 선박 등이 조난 시에 탐색구조(SAR: Search and Rescue) 활동을 도울 수 있도록 조난경보와 위치정보를 제공하는 시스템이다. COSPAS-SARSAT 서비스의 경우, 조난신호 접수에서 조난위치확정까지 평균 1시간 이상이 소요되고, 위치정확도가 수 Km 정도로 범위가 넓은 편이다. 이러한 문제점을 개선하기 위해서 중궤도 위성을 이용한 차세대 탐색구조 시스템 개발이 추진 중에 있으며 EU에서 2011년 FOC(Full Operation Capability)를 목표로 개발중인 갈릴레오 항법위성 프로젝트의 경우 SAR 중계기를 탑재하여 탐색구조 서비스를 제공할 계획에 있다. 갈릴레오 탐색구조(SAR/Galileo) 서비스는 수 m급의 위치정확도, 10분 이내의 조난신호 접수에서 구조까지 소요시간, 및 조난자에게 회신링크 서비스 제공 등 보다 향상된 탐색구조 성능을 제공하기 위해 개발 중에 있으므로, 갈릴레오 위성 서비스가 시작되면 탐색구조시스템 체계에 보다 신속하고 정확한 구조가 가능할 것으로 예상된다. 우리나라에서는 COSPAS-SARSAT 회원국으로 가입하여 현재 송도 해양경찰청 내에 LEOLUT와 MCC가 설치되어 운용되고 있다. 날로 더해가는 다양한 재난에 대한 인명구조를 신속하고 효과적으로 대처하기 위해 차세대 갈릴레오 탐색구조 지상국 도입이 절실하다고 할 수 있다. 따라서, 탐색구조 단말기를 포함한 지상국 인프라의 구축 등 갈릴레오 탐색구조 지상시스템 개발의 참여 방안에 관한 연구는 매우 시기적절하고 중요한 연구이다. 본 논문은 갈릴레오 사업에 참여하여 SAR/Galileo 개발을 주관하고 있는 중국의 사례를 분석함으로 우리나라가 차세대 갈릴레오 탐색구조 지상시스템 개발에 참여하기 위해서 필요한 참여방법 및 절차 등을 도출하고, 참여 가능한 개발범위, 참여전략 및 추진체계에 대해서 제안한다.법의 성능을 평가를 위하여 원본 여권에서 얼굴 부분을 위조한 여권과 기울어진 여권 영상을 대상으로 실험한 결과, 제안된 방법이 여권의 코드 인식 및 얼굴 인증에 있어서 우수한 성능이 있음을 확인하였다.진행하고 있다.태도와 유아의 창의성간에는 상관이 없는 것으로 나타났고, 일반 유아의 아버지 양육태도와 유아의 창의성간의 상관에서는 아버지 양육태도의 성취-비성취 요인에서와 창의성제목의 추상성요인에서 상관이 있는 것으로 나타났다. 따라서 창의성이 높은 아동의 아버지의 양육태도는 일반 유아의 아버지와 보다 더 애정적이며 자율성이 높지만 창의성이 높은 아동의 집단내에서 창의성에 특별한 영향을 더 미치는 아버지의 양육방식은 발견되지 않았다. 반면 일반 유아의 경우 아버지의 성취지향성이 낮을 때 자녀의 창의성을 향상시킬 수 있는 것으로 나타났다. 이상에서 자녀의 창의성을 향상시키는 중요한 양육차원은 애정성이나 비성취지향성으로 나타나고 있어 정서적인 측면의 지원인 것으로 밝혀졌다.징에서 나타나는 AD-SR맥락의 반성적 탐구가 자주 나타났다. 반성적 탐구 척도 두 그룹을 비교 했을 때 CON 상호작용의 특징이 낮게 나타나는 N그룹이 양적으로 그리고 내용적으로 더 의미 있는 반성적 탐구를 했다용을 지원하는 홈페이지를 만들어 자료 제공 사이트에 대한 메타 자료를 데이터베이스화했으며 이를 통해 학생들이 원하는 실시간 자료를 검색하여 찾을 수 있고 홈페이지를 방분했을 때 이해하기 어려운 그래프나 각 홈페이지가 제공하는 자료들에 대한 처리 방법을 도움말로 제공받을 수 있게 했다. 실시간 자료들을 이용한 학습은 학생들의 학습 의욕과 탐구 능력을 향상시켰으며 컴퓨터 활용 능력과 외국어 자료 활용 능력을 향상 시키는데도 도움을 주었다.지역산업 발전을 위한 기술역량이 강화될 것이다.정 ${\rightarrow}$ 분배 ${\rightarrow}$ 최대다수의 최대행복이다.는 역할을 한다. 따라

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Verification of safety integrity for vital data processing device through quantitative safety analysis (정량적 안전성 분석을 통한 Vital 데이터 처리장치의 안전무결성 요구사항 검증)

  • Choi, Jin-Woo;Park, Jae-Young
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.7
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    • pp.4863-4870
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    • 2015
  • Currently, as a priority to secure the safety of the railway signalling system, verification for satisfy of the safety integrity requirements(SIR) is required to the essential elements. Safety Integrity Requirements(SIR) verification is performed based on the system safety analysis. But the probability of securing basic data for system safety analysis significantly dropped because there is no experience yet performed in the country. Therefore we are had to rely on a qualitative analysis. There are methods such as qualitative risk analysis matrix, and risk graphs. The qualitative analysis is wide, the width of the accident. However, the reliability of the result is significantly less has a disadvantage. Therefore, it should be parallel quantitative safety analysis of the system/products in order to compensate for the disadvantages of the qualitative analysis. This paper presents a quantitative safety analysis method to overcome the disadvantages of the qualitative analysis. And through a result, highly reliable Safety Integrity Requirements(SIR) verification measures proposed. Verification results, the dangerous failure incidence for vital data processing device was calculated to be $1.172279{\times}10^{-9}$. The result was verified to exceed the required safety integrity targets more.

Voltage-Frequency-Island Aware Energy Optimization Methodology for Network-on-Chip Design (전압-주파수-구역을 고려한 에너지 최적화 네트워크-온-칩 설계 방법론)

  • Kim, Woo-Joong;Kwon, Soon-Tae;Shin, Dong-Kun;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.22-30
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    • 2009
  • Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.