• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.522-529
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• 2007

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of $1/3{\times}f_{in}\;and\;f_{in}$ tones, while dissipating 29 mA from 4.1 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1321-1327
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• 2009

In this paper, as the mobile communication service is widely used and the demand for wireless repeaters is rapidly increasing because of the easiness of extending service areas. But a wireless repeater has a problem the oscillation due to feedback signal. We proposed a new hybrid interference canceller using the adaptive filter with CMA(Constant Modulus Algorithm)-Grouped LMS(Least Mean Square) algorithm in the adaptive interference canceller. The proposed interference canceller has better channel adaptive performance and a lower MSE(Mean Square Error) than conventional structure because it uses the cancellation method of Grouped LMS algorithm. The proposed detector uses the LMS algorithms with two different step size to reduce mean square error and to obtain fast convergence. This structure reduces the number of iterations for the same MSE performance and hardware complexity compared to conventional nonlinear interference canceller.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.491-498
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• 2012

Recently, many papers have been proposed in order to improve the OFDM system performance in T-DMB DOCR (Digital On Channel Repeater), by using removing the feedback signal so that the transmitter power can be increased or by using the equalizer to remove ICI. Despite these efforts, however, signal quality at the receiving terminal has not been improved because of constellation smearing in T-DMB DOCR. In this paper, in order to suppress constellation smearing, we propose an effective equalizer algorithm that can improve system performance. We perform adaptive channel estimation and non-coherent decision directed noise cancellation method that can estimate the channel subsequently during data symbols period in the frequency domain. So we can obtain better quality of the signal at the receiving terminal. In order to secure QoS(Quality of Service) required in T-DMB handsets, we evaluate SNR and BER in T-DMB DOCR(Digital On Channel Repeater) and verified by simulation. In this simulation results, this system is satisfied the performance of BER=$10^{-5}$ at less than SNR=14 dB at the receiver after compensation of phase noise -18 dBc.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.1
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• pp.123-132
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• 1999

In this paper, a quadratic sigmoid neural equalizer(QSNE) is proposed to improve the performance of conventional neural equalizer in terms of bit error probability by using a quadratic sigmoid function as the activation function of neural networks. Conventional neural equalizers which have been used to compensate for nonlinear distortions adopt the sigmoid function. In the case of sigmoid neural equalizer, each neuron has one linear decision boundary. So many neurons are required when the neural equalizer has to separate complicated structure. But in case of the proposed QSNF and quadratic sigmoid neural decision feedback equalizer(QSNDFE), each neuron separates decision region with two parallel lines. Therefore, QSNE and QSNDFE have better performance and simpler structure than the conventional neural equalizers in terms of bit error probability. When the proposed QSNDFE is applied to communication systems and digital magnetic recording systems, it is an improvement of approximately 1.5dB~8.3dB in signal to moise ratio(SNR) over the conventional decision feedback equalizer(DEF) and neural decision feedback equalizer(NDFE). As intersymbol interference(ISI) and nonlinear distortions become severer, QSNDFE shows astounding SNR shows astounding SNR performance gain over the conventional equalizers in the same bit error probability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.103-118
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• 1999

This paper analyzes the performance of symbol timing recovery and equalizer in 8VSB digital terrestrial TV receiver under various multipath signals and proposes equalization techniques which improve indoor reception performance. Data segment sync is used for symbol timing recovery and timing offset is measured for echoes of various delays and amplitudes by using symbol timing detection filter whose pattern is +1. +1. -1. and -1. Measured timing offsets were below 10% for long echoes with more than 5 symbol delay and above 30% for short echoes with around 1 symbol delay. Indoor reception is always more challenging than outdoor reception due to lower signal strength. large and short multipaths. and moving interfering objects. So it is considered to use FSE (Fractionally Spaced Equalizer) which is very robust to timing offset and blind equalizer which can update equalizer tap coefficients even by information data. We compare the performance of conventional DFE (Decision Feedback Equalizer) and FSE-DFE using LMS algorithm and Stop and Go algorithm for the indoor reception. Experiments reveals FSE has excellent performance for large timing offset and Stop and Go algorithm shows good performance for Doppler shift. so we propose to use FSE-DFE structure with Stop and Go algorithm for the reliable indoor reception.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.4
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• pp.481-488
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• 2011

In this paper, we study a novel wireless interference cancellation system(ICS) repeater based on OFDM system with phase noise analysis and performance evaluation. Recently, there were many researches about wireless repeater. The previous study is just considering the feedback channel cancellation algorithm. But, in wireless repeater system, the phase noise effect can exist at up and down converter of wireless repeater. In wireless repeater system, if there are phase noise effects, the performance of system will get worse. So, the phase noise compensator is needed in wireless repeater. Therefore, we propose adaptive phase noise compensator based on OFDM system in order to effectively cancel phase noise. In order to cancel interference, we adapt adaptive phase noise compensator in wireless repeater system. The adaptive phase noise compensator compensates phase noise effect. Therefore, in this paper, we analyze phase noise of wireless repeater based on OFDM system. In this paper, when phase noise power is -15 dBc and phase noise cutoff frequency is 100 kHz at 4QAM, the BER performance of propose algorithm is better about 4 dB than with adaptive equalizer and without phase noise compensator at $10^{-4}$.

• Korean Journal of Optics and Photonics
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• v.32 no.1
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• pp.1-8
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• 2021

We have studied a tiled-aperture coherent-beam-combining system based on constructive interference, as a way to overcome the power limitation of a single laser. A 1-watt-level, 3-channel coherent fiber laser and a 3-channel fiber array of triangular tiling with tip-tilt function were developed. A monitoring system, phase controller, and 3-channel phase modulator formed a closed-loop control system, and the SPGD algorithm was applied. Eventually, phase-locking with a rate of 5-67 kHz and peak-intensity efficiency comparable to the ideal case of 53.3% was successfully realized. We were able to develop the essential elements for a tiled-aperture coherent-beam-combining system that had the potential for highest output power without any beam-combining components, and a multichannel coherent-beam-combining system with higher output power and high speed is anticipated in the future.