• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.174-184
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• 2001

Wavelength tunable fiber ring laser can be tuned by causing a resonance on the optical path having the least loss which is controlled by a polarization adjustment. It is observed that lasing wavelengths having 1 nm FSR(Free Spectral Range) can be tuned over the range of 1540~1560 nm when a polarization controller and an intra-cavity polarizer are adjusted. The tuning mechanism can be expected by analyzing the characteristics of the laser output using an optical path model and the concept of a birefringence loss. It is found that the constructive interference between longitudinal modes of different optical paths may cause wavelength tuning in the fiber ring laser.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.175-180
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• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.145-148
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• 2016

In this paper, we propose a design of Intra Prediction angular mode decision for high-performance HEVC encoder. Intra Prediction works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original image pixel, using an algorithm that determines Angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9k and operating speed is 2GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Journal of the Korea Organic Resources Recycling Association
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• v.16 no.4
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• pp.57-63
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• 2008

The characteristics of the bio-oil produced by the pyrolysis process with pig feces was investigated in this paper. The continuous auger-type reactor produced bio-oil was maintained at the temperature range of 400 to $600^{\circ}C$, which was higher than a typical that in a conventional pyrolysis system. The pig feces was used as the feedstock. The bio-oil and its compositions were characterized by water analysis, heating values, elemental analysis, bio-oil compounds, by Gas Chromatography/Mass Spectrometry (GC/MS), and functional group by $^1H$ NMR spectroscopy. It was found that the maximum bio-oil yields of 21% w.t. was achieved at $550^{\circ}C$. This result suggested that this auger reactor might be a potential technology for livestock waste treatment to produce bio-oil because it is able to be improved to reach higher efficiency of bio-oil production in further study. The pyrolysis system reported herein had low heat transfer into the feedstock in the auger reactor so that it needs improve the heat conduction rate of the system in further study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.329-334
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• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.391-398
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• 2004

Far-ultraviolet Imaging Spectrograph (FIMS) is the main payload of the Korea's first scientific micro satellite STSAT-1, which was launched at Sep. 27 2003 successfully. Major objective of FIMS is observing hot gas in the Galaxy in FUV bands to diagnose the energy flow models of the interstellar medium. Supernova remnants, molecular clouds, and Aurora emission in the geomagnetic pole regions are specific targets for pointing observation. Although the whole system was calibrated before launch, it is essential to perform on-orbit calibration for data analysis. For spectral calibration, we observed airglow lines in the atmosphere since they provide good spectral references. We identify and compare the observed airglow lines with model calculations, and correct the spectral distortion appeared in the detector system to improve the spectral resolution of the system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.953-958
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• 2013

In this paper, an efficient hardware architecture is proposed for $32{\times}32$ inverse transform HEVC decoder. HEVC is a new image compression standard to deal with much larger image sizes compared with conventional image codecs, such as 4k, 8k images. To process huge image data effectively, it adopts various new block structures. Theses blocks consists of $4{\times}4$, $8{\times}8$, $16{\times}16$, and $32{\times}32$ block. This paper suggests an effective structures to process $32{\times}32$ inverse transform. This structure of inverse transform adopts the decomposed $16{\times}16$ matrixes of $32{\times}32$ matrix, and simplified the operations by implementing multiplying with shifters and adders. Additionally the operations frequency is downed by using multicycle paths. Also this structure can be easily adopted to a multi-size transform or a forward transform block in HEVC codec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.