• Journal of Digital Convergence
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• v.12 no.10
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• pp.317-327
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• 2014

To improve the efficiency of wireless channel, IEEE 802.11ac uses the DL MU-MIMO MAC scheme through which an AP transmits multiple frames to different mobile nodes simultaneously. IEEE 802.11ac DL MU-MIMO MAC needs a new step, called as TXOP sharing, between legacy IEEE 802.11n DL SU-MIMO's two operations, the obtaining an EDCA TXOP and the transmitting multiple frames for EDCA TXOP. In the TXOP sharing operation, both wireless channel destinations and frames transmitted for its TXOP period should are determined. So this paper deals with the TXOP sharing for improving IEEE 802.11ac MAC performance. However, the EDCA priority based method mentioned by IEEE 802.11ac standard document not fair among the buffers and the frames of buffers, and occurs in high_loss rate and high_delay about specific buffers. In this paper, we propose a new scheme of the TXOP sharing with sequencing p-AC, s-AC in similar properties, and all S-AC. This method provides a differentiated service without damage of EDCA characteristics.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.4
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• pp.665-670
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• 2020

Buffer layer in CIGS thin-film solar cells improves energy conversion efficiency through band alignment between the absorption layer and the window layer. ZnS is a non-toxic II-VI compound semiconductor with direct-transition band gaps and n-conductivity as well as with excellent lattice matching for CIGS absorbent layers. In this study, the structural and optical properties of ZnS thin films, deposited by RF magnetron sputtering method and subsequently performed by the rapid thermal annealing treatment, were investigated for the buffer layer. The zincblende cubic structures along (111), (220), and (311) were shown in all specimens. The rapid thermal annealed specimens at the relatively low temperatures were polycrystalline structure with the wurtzite hexagonal structures along (002). Rapid thermal annealing at high temperatures changed the polycrystalline structure to the single crystal of the zincblende cubic structures. Through the chemical analysis, the zincblende cubic structure was obtained in the specimen with the ratio of Zn/S near stoichiometry. ZnS thin film showed the shifted absorption edge towards the lower wavelength as annealing temperature increased, and the mean optical transmittance in the visible light range increased to 80.40% under 500℃ conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.363-363
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• 2013

태양광 발전산업에서 현재 주류인 결정 실리콘 태양전지의 변환효율은 꾸준히 향상되고 있으나, 태양전지의 가격이 매년 서서히 하강되고 있는 실정에서 결정질 실리콘 가격의 상승 등으로 부가가치 창출에 어려움이 있으며, 생산 원가를 낮출 수 있는 태양전지 제조기술로는 2 세대 태양전지로 불리는 박막형이 현재의 대안이며, 특히 에너지 변환 효율과 생산 원가에서 장점이 있는 것이 CIGS 박막 태양전지로 판단된다. 화합물반도체 베이스인 CIGS 박막태양전지는 연구실에서는 세계적으로 20.3% 높은 효율을 보고하고 있으며, 모듈급에서도 13% 효율로 생산이 시작되고 있다. 국내에서도 연구실 규모 뿐만 아니라 대면적(모듈급) CIGS 박막태양전지 증착용 장비, 제조공정 등의 기술개발이 진행되고 있다. CIGSe2를 광흡수층으로 하는 CIGSe2 박막 태양전지의 구조는 여러 층의 단위박막(하부전극, 광흡수층, 버퍼층, 상부투명전극)을 순차적으로 형성시켜 만든다. 이중에 소다라임유리를 기판으로 하는 하부전극은 Mo 재료를 스퍼터링 방법으로 증착하여 주로 사용한다. 하부전극은 우수한 전기적 특성이 요구되며, 주상조직으로 성장하여야 하며, 고온 안정성 확보를 위하여 기판과의 밀착성이 좋아야하고 또한 레이저 패턴시 기판에서 잘 떨어져야 하는 특성을 동시에 가져야 한다. 본 연구에서는 대면적 CIGSe2 박막태양전지에서 요구되는 하부전극 Mo 박막의 제작과 그 특성에 대해 평가하고, 최종적으로 대면적 CIGSe2 박막태양전지 공정에 적용 그 결과를 논하고자 한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.403-409
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• 2013

In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.91-101
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• 2012

Automobile manufacturing consists of body-line, painting-line, and assembly-line. These production lines are disposed in series and go through a flow process, so according to the status of pre & post processing, a suspension happens in a line by a starvation(impossibility of production by insufficient supply) or blocking(impossibility of production by exceed capacity). Therefore, to prevent a loss of production coming from a starvation or blocking, a storage such as WBS or PBS is independently owned and operated. The paper suggests the simulation model of integrated storage which can operate it by integrating each storage performing a role as a buffer of line. Specifically, the paper found the answers about reasonable number of Stacker Crane and AGV(Automatic Guided Vehicle) and suggested a methodology of operation which is available to operate them. Also, it compared an efficiency between a model of current storage and integrated storage through simulation. As a result, it turned out that the model suggested in the paper was more efficient on suspension of painting-line stop than a current storage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.362-363
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• 2011

태양광 발전산업에서 현재 주류인 결정 실리콘 태양전지의 변환효율은 꾸준히 향상되고 있으나, 태양전지의 가격이 매년 서서히 하강되고 있는 실정에서 결정질 실리콘 가격의 상승 등으로 부가가치창출에 어려움이 있으며, 생산 원가를 낮출 수 있는 태양전지 제조기술로는 2세대 태양전지로 불리는 박막형이 현재의 대안이며, 특히 에너지 변환 효율과 생산 원가에서 장점이 있는 것이 CIGS 박막태양전지로 판단된다. 화합물반도체 베이스인 CIGS 박막태양전지는 연구실에서는 세계적으로 20.3% 높은 효율을 보고하고 있으며, 모듈급에서도 13% 효율로 생산이 시작되고 있다. 국내에서도 연구실 규모뿐만 아니라 대면적(모듈급) CIGS 박막 태양전지 증착용 장비, 제조공정 등의 기술개발이 진행되고 있다. CIGSe2를 광흡수층으로 하는 CIGSe2 박막 태양전지의 구조는 여러 층의 단위박막(하부전극, 광흡수층, 버퍼층, 상부투명전극)을 순차적으로 형성시켜 만든다. 본 연구에서 광흡수층은 스퍼터링 방법으로 CIG precusor를 먼저 만들고, 그 위에 증발법으로 Se를 증착한 다음, 열처리 조건으로 CIGSe2 박막태양전지를 제작하였다. 제작된 CIGSe2 박막태양전지는 열처리 조건에 따라서 에너지 변환효율이 3.3에서 9.5%까지 다양하게 측정되었으며, 본 연구의 최고효율이 측정된 디바이스에서 개방전압은 0.48 V, 전류밀도는 33 mA/cm였으며, 그리드 전극을 제외한 디바이스의 면적은 0.57 cm2였다. 본 연구에서는 셀렌화 열처리 조건에 따른 CIGSe2 박막태양전지의 효율 측면을 고려하였지만, 더 높은 에너지 변환효율을 갖기 위해서 좀 더 높은 에너지 밴드갭과 개방전압, 낮은 직렬저항과 높은 shunt 저항 값 등의 상호 의존성에 대해서 연구결과들을 논하고자 한다.

• Journal of Digital Contents Society
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• v.10 no.2
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• pp.357-365
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• 2009

To effectively exploit the underlying network bandwidth while maximizing user perceivable QoS, mandatory to make proper estimation on packet loss and queuing delay of the underling network. This issue is further emphasized in wireless network environment where network bandwidth is scarce resource. In this work, we focus our effort on developing performance model for wireless network. We collect packet trace from actually wireless network environment. We find that packet count process and bandwidth process in wireless environment exhibits long range property. We extract key performance parameters of the underlying network traffic. We develop an analytical model for buffer overflow probability and waiting time. We obtain the tail probability of the queueing system using Fractional Brown Motion (FBM). We represent average queuing delay from queue length model. Through our study based upon empirical data, it is found that our performance model well represent the physical characteristics of the IEEE 802.11b network traffic.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.127-132
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• 2018

In this paper, a high conversion gain cascode mixer was designed in W-band and verified by the fabrication and measurements. In the high frequency band such as a W-band, the conversion loss of a mixer is increased because of the poor performance of transistors. This high conversion loss of the mixer requires additional circuits which can give an extra gain such as an RF buffer amplifier, and this can affects the linearity and stability of the overall systems. Therefore, it is necessary to maximize the conversion gain of the mixer. To maximize the conversion gain of the mixer, biases of the transistor were optimized, and output load impedance was optimized by the load-pull simulations. The designed mixer was fabricated in $0.1-{\mu}m$ GaAs pHEMT technology and verified by the measurements. The measurement results shows a maximum conversion gain of -4.7 dB at W-band and an input 1-dB compression point of 2.5 dBm.