• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.5
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• pp.499-503
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• 2016

We study algorithms that can efficiently find cube roots by modifying Cipolla-Lehmer algorithm. In this paper, we present two type algorithms for finding cube roots in finite field, which improves Cipolla-Lehmer algorithm. If the number of multiplications of two type algorithms has a little bit of a difference, then it is more efficient algorithm which have less storage variables.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1297-1308
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• 2006

Multiplications in finite fields are one of the most important arithmetic operations for implementations of elliptic curve cryptographic systems. In this paper, we propose a new multiplication algorithm and VLSI architecture over $GF(2^m)$ using Gaussian normal basis. The proposed algorithm is designed by using a symmetric property of normal elements multiplication and transforming coefficients of normal elements. The proposed multiplication algorithm is applicable to all the five recommended fields $GF(2^m)$ for elliptic curve cryptosystems by NIST and IEEE 1363, where $m\in${163, 233, 283, 409, 571}. A new VLSI architecture based on the proposed multiplication algorithm is faster or requires less hardware resources compared with previously proposed normal basis multipliers over $GF(2^m)$. In addition, we gives an easy method finding a basic multiplication matrix of normal elements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2341-2349
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• 2015

The commonly used Goldschmidt's floating-point divider algorithm performs two multiplications in one iteration. In this paper, a tentative error corrected K'th Goldschmidt's floating-point number divider algorithm which performs K times multiplications in one iteration is proposed. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation in single precision and double precision divider is derived from many reciprocal tables with varying sizes. In addition, an error correction algorithm, which consists of one multiplication and a decision, to get exact result in divider is proposed. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a divider unit. Also, it can be used to construct optimized approximate reciprocal tables.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.289-300
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• 2001

본 논문에서는 유한 필드 GF(2$_{m}$ ) 상에서 모듈러 곱셈 A($\chi$)B($\chi$) mod P($\chi$)을 수행하는 새로운 선형 문제-크기(full-size) 시스톨릭 어레이 구조인 LSB-first 곱셈기를 제안한다. 피연산자 B($\chi$)의 LSB(least significant bit)를 먼저 사용하는 LSB-first 모듈러 곱셈 알고리즘으로부터 새로운 비트별 순환 방정식을 구한다. 데이터의 흐름이 규칙적인 순환 방정식을 공간-시간 변환으로 새로운 시스톨릭 곱셈기를 설계하고 분석한다. 기존의 곱셈기와 비교할 때 제안한 곱셈기의 면적-시간 성능이 각각 10%와 18% 향상됨을 보여준다. 또한 같은 설계방법으로 곱셈과 제곱연산을 동시에 수행하는 새로운 시스톨릭 곱셈/제곱기를 제안한다. 유한 필드상의 지수연산을 위해서 제안한 시스톨릭 곱셈/제곱기를 사용할 때 곱셈기만을 사용 할 때보다 면적-시간 성능이 약 26% 향상됨을 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1928-1934
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• 1993

This paper presents a fast algorithm of integer discrete cosine transform(IDCT) allowing VLSI implementation by integer arithmetic. The proposed fast algorithm has been developed using Chen`s matrix decomposition in DCT, and requires less number of arithmetic operations compared to the IDCT. In the presented algorithm, the number of addition number is the same as the one of Chen`s algorithm if DCT, and the number of multiplication if the same as that in DCT at N=8 but drastically decreasing when N is above 8. In addition, the drawbacks of DCT such as performance degradation at the finite length arithmetic could be overcome by the IDCT.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.605-607
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• 2000

본 논문에서는 유한 필드 GF(2m)상에서 모듈러 곱셈 A(x)B(x) mod p(x)를 수행하는 2-디지트 시리얼 (2-digit-serial) 시스톨릭 어레이 구조인 곱셈기를 제안하였다. LSB-first 곱셈 알고리즘을 분석한 후 2-디지트 시리얼 형태의 자료의존 그래프(data dependency graph, 이하 DG)를 생성하여 시스톨릭 어레이를 설계하였다. 제안한 구조는 정규적이고 서로 반대 방향으로 진행하는 에지들이 없다. 그래서 VLSI 구현에 적합하다. 제안한 2-디지트 시리얼 곱셈기는 비트-패러럴(bit-parallel) 곱셈기 보다는 적은 하드웨어를 사용하며 비트-시리얼(bit-serial) 곱셈기 보다는 빠르다. 본 논문에서 제안한 2-디지트 시리얼 시스톨릭 곱셈기는 기존의 같은 종류의 곱셈기 보다 처리기의 최대 지연 시간이 적다. 그러므로 전체 시스톨릭 곱셈기의 처리시간을 향상시킬 수 있다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.670-672
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• 1999

소인수 분해 문제 혹은 이산대수 문제의 어려움에 근거한 공개키 암호 시스템에서는 큰 수에 대한 모듈라 멱승연산이 전체 시스템의 속도를 좌우하는 큰 요인이 된다. 모듈라 멱승 연산은 모듈라 곱셈으로 이루어진 연산이므로 모듈라 곱셈의 횟수를 줄이거나 빠른 모듈라 곱셈을 이용하면 멱승 연산의 계산 속도가 향상한다. 모듈라 곱셈 방법 중에서도 메모리를 적게 사용하면서도 고속인 방법들을 골라 비교하여 본다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.575-577
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• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1044-1051
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• 2020

The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.