• Title/Summary/Keyword: 고장격리율

Search Result 3, Processing Time 0.019 seconds

Improvements in Design and Evaluation of Built-In-Test System (무기체계 정비성 향상을 위한 BIT 설계 및 검증 방안)

  • Heo, Wan-Ok;Park, Eun-Shim;Yoon, Jung-Hwan
    • Journal of the Korea Institute of Military Science and Technology
    • /
    • v.15 no.2
    • /
    • pp.111-120
    • /
    • 2012
  • Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

Built-In-Test Coverage Analysis Considering Failure Mode of Electronics Components (전자부품 고장모드를 고려한 Built-In-Test 성능분석)

  • Seo, Joon-Ho;Ko, Jin-Young;Park, Han-Joon
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.43 no.5
    • /
    • pp.449-455
    • /
    • 2015
  • Built-In-Test(hereafter: BIT) is necessary functionality for aircraft flight safety and it requires a high failure detection capacity of more than 95 % in the case of avionics equipment. The BIT coverage analysis is needed to make sure that BIT meets its fault diagnosis capability. FMECA is used a lot of for the BIT coverage analysis. However, in this paper, the BIT coverage analysis based on electronic components is introduced to minimize the analytical error. Further, by applying the failure mode of the electronic components and excluding electronic components that do not affect flight safety, the BIT coverage analysis can be more accurate. Finally, BIT demo was performed and it was confirmed that the performance of the actual BIT matches the analysis of BIT performance.

Redundancy Management Design for Triplex Flight Control System (3중 비행제어시스템의 다중화 기법 설계)

  • Park, Sung-Han;Kim, Jae-Yong;Cho, In-Je;Hwang, Byung-Moon
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.38 no.2
    • /
    • pp.169-179
    • /
    • 2010
  • Satisfying the same probability of loss of control and essentially two fail operative performance with a triplex computer architecture requires a lot of modification of the conventional redundancy management design techniques, previously employed in quadruplex digital flight control computer. T-50 FCS for triplex redundancy management design applied an advanced digital flight control architecture with an I/O controller which is functionally independent of the digital computer to achieve the same reliability and special failure analysis and isolation schemes for fail operational goals with a triplex configuration. The analysis results indicated that the triplex flight control system is to satisfy the safety requirement utilizing the advanced flight control techniques and the system performance of the implemented flight control system was verified by failure mode effect test.