• The Journal of the Acoustical Society of Korea
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• v.41 no.2
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• pp.166-173
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• 2022

In this paper, the performance of joint equalizer and phase-locked loop in underwater communications is analyzed. In the channel where the Doppler frequency exists, it is difficult to recover the transmitted data only by the equalizer. To compensate for the Doppler frequency, the phase-locked loop is used. For removing the time-varying multipath and the Doppler frequency simultaneously, the equalizer and the phase-locked loop operate jointly. Also, if the initial Doppler frequency error obtained by Fast Fourier Transform (FFT) is compensated, the convergence speed of the joint equalizer and phase-locked loop can be improved. To verify the performance, lake and sea experiments were conducted. As a result, it was showed that the joint equalizer and phase-locked loop converges sufficiently in the preamble (known data) period regardless of whether the Doppler frequency is compensated or not. And, the bit error in random data period is not occurred. However, we can increase the convergence speed of the equalizer more than twice through the compensation of Doppler frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.