• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1317-1328
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• 1996

In this paper, we propose a fast image coding algorithm to shorten long time to take on fractal image encoding. For its Performance evaluation, the algorithm compares with other traditional fractal coding methods. In the traditional fractal image coding methods, an original image is contracted by a factor in order to make the corresponding image to be compared with. Them, the whole area of the contracted image is searched in order to find the fixed point of contractive transformation of the orignal image corresponding to the contracted image. It needs a lot of searching time on encoding However, the proposed algorithm considerable reduces encoding time by using scaling method and limited search area method. On comparison of the proposed algorithm with Joaquin's method, the proposed algorithm is at least 180 times as fast as that of Jacquin's method on encoding time with a little degradation of the decoded image quality and a little increase of the compression rate. There-for, it is found that the proposed algorithm largely improves the performance in the aspect of encoding time when compared with other fractal image coding methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.6
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• pp.9-15
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• 2007

In this paper, we propose an efficient method for Processing DWT (Discrete Wavelet Transform) on GPU (Graphics Processing Unit). Since the DWT and EBCOT (embedded block coding with optimized truncation) are the most complicated submodules in JPEG2000, we design a high-performance processing framework for performing DWT using the fragment shader of GPU based on the render-to-texture (RTT) architecture. Experimental results show that the performance increases significantly, in which DWT running on modern GPU is more than 10 times faster than on modern CPU. Furthermore, by replacing the DWT part of Jasper which is the JPEG2000 reference software, the overall processing is 2$\sim$16 times faster than the original JasPer. The GPU-driven render-to-texture architecture proposed in this paper can be used in the general image and computer vision processing for high-speed processing.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.658-667
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• 2004

For digital image compression, various fractal image coding schemes using the self-similarity of image have been studied extensively. This paper discusses the problem that occurs during the calculating process of adaptive orthogonal transformation and provides improvements of LIFS coding scheme using the transformation. This proposed scheme has a better performance than JPEG for a wide range of compression ratio. This research also proposes an image composition method consisting of all domains of the transformation. The results show that the arithmetic operation processes of the encoder and the decoder become much smaller even without the distortion of the coding performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.66-74
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• 2008

Surveillance system using active tracking camera has no distance limitation of surveillance range compared to supersonic or sound sensors. However, complex motion tracking algorithm requires huge amount of computation. Compared to conventional methods using DSPs or embedded processors, this paper proposes and implements a novel motion tracker unit that detects and extracts motion information of moving objects by using picture difference of consecutive frames. The proposed motion tracker unit was implemented in FPGA with about 13,000 gates. It processes NTSC format video and was verified by embedding it into the active surveillance camera system. We also propose and implements a motion estimator unit linkable to video codec by embedding the proposed motion tracker unit into ready-made motion estimator unit. The implemented motion estimator unit is about 17,000 gates in $0.35{\mu}m$ process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.925-931
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• 2008

In video coding standard H.264/AVC, variable block size mode algorithm improves compression efficiency but has need of a large amount of computation for various block modes and mode decision. Meanwhile, decided inter block modes depend on the complexity of a block image, and then the more complex a macroblock is, the smaller its block size is. This paper proposes fast inter block mode decision algorithm. It limits valid block modes to the block modes with a great chance for decision using the image complexity and carries out motion estimation rate-distortion optimization with only the valid block modes. In addition to that, it applies fast motion estimation PDE to the valid block modes with only the $16{\times}16$ block mode. The reference software JM 9.5 was executed to estimate the proposed algorithm's performance. The simulation results showed that the proposed algorithm could save about 24.12% of the averaged motion estimation time while keeping the image quality and the bit rate to be -0.02dB and -0.12% on the average, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.434-440
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• 2003

Since Jacquine introduced the image coding algorithm using fractal theory, many fractal image compression algorithms providing good quality at low bit rate have been proposed by Fisher and Beaumount et al.. But a problem of the previous implementations is that the decoding rests on an iterative procedure whose complexity is image-dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and an input image to be encoded. As the decoding process can be completed with received fractal coefficients and predefined initial image without repeated iterations, the decoding time could be remarkably reduced.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.671-673
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• 1998

전력 및 전화 서비스와 같은 저속의 댁내 망 구축에서 서비스 품질을 보장하는 다양한 대역폭의 멀티미디어 및 멀티포인트 서비스를 효율적으로 제공할 수 있는 댁내 망 구축 및 동영상 압축 기술 및 디지털 신호처리 기술의 발전으로 인해 댁내의 디지털 가전 기기들이 고속의 통신 기능이 탑재되는 정보 가전으로 발전하고 있다. 본 논문에서는 현재 활발히 다양한 댁배 망 서비스를 제공하고 잇는 RBB서비스 제공자들의 현황을 알아보고, 액세스 망을 통한 서비스와 댁내에서의 통신 서비스를 제공하기 위해서 댁내 망이 갖추어야할 조건을 분석한다. 또한, 앞으로 댁내 망 일반 사용자들이 이용하게 될 댁내외 서비스를 만족시키기 위한 서비스 요구사항에 대하여 기술한다.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1952-1955
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• 2003

최근에 표준화된 H.264 의 인트라 예측은 I-프레임을 압축하는데 사용된다. 최대의 코딩효율을 위해서 부호화기는 모든 인트라 예측 모드를 반복적으로 찾는다. 그러나 이것은 H.264 의 부호화기 복잡도를 매우 크게 하는 단점이 있다. 모든 경우의 모드중에 영상에 따라서는 특히 그 발생 가능성이 높거나 낮은 경우의 모드가 발생한다. 본 논문에서는 에지맵을 이용하여 H.264 의 인트라 예측 모드를 선별적으로 선택하는 방법을 제안한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.111-114
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• 1997

동영상 압축 알고리즘에서 움직임 추정기법은 매우 중요한 역할을 담당하는 반면, 수행시간이나 하드웨어 구현에 어려움이 많아 이를 개선하기 위한 알고리즘들이 개발되어 왔다. 본 논문에서는 적절한 화소 분류를 통해 우수한 화질과 적은 계산량, 간단한 하드웨어 구조를 가지는 새로운 움직임 추정기법을 제안한다. 기존의 1-비트 화소 분류 방법에서 변형된 새로운 비용 함수를 이용한 2-비트, 3-비트 화소 분류 방법과 2차 비용함수를 이용한 화소 분류 방법을 제안한다. 또한 여러 고속 움직임 추정 알고리즘과도 쉽게 연결하여 사용할 수 있으며 우수한 성능을 나타내는 것을 모의 실험을 통해 보였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.