• Title/Summary/Keyword: 고속 스윗칭

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Design and Analsis of a high speed switching system with two priority (두개의 우선 순위를 가지는 고속 스윗칭 시스템의 설계 및 성능 분석)

  • Hong, Yo-Hun;Choe, Jin-Sik;Jeon, Mun-Seok
    • The KIPS Transactions:PartC
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    • v.8C no.6
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    • pp.793-805
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    • 2001
  • In the recent priority system, high-priority packet will be served first and low-priority packet will be served when there isn\`t any high-priority packet in the system. By the way, even high-priority packet can be blocked by HOL (Head of Line) contention in the input queueing System. Therefore, the whole switching performance can be improved by serving low-priority packet even though high-priority packet is blocked. In this paper, we study the performance of preemptive priority in an input queueing switch for high speed switch system. The analysis of this switching system is taken into account of the influence of priority scheduling and the window scheme for head-of-line contention. We derive queue length distribution, delay and maximum throughput for the switching system based on these control schemes. Because of the service dependencies between inputs, an exact analysis of this switching system is intractable. Consequently, we provide an approximate analysis based on some independence assumption and the flow conservation rule. We use an equivalent queueing system to estimate the service capability seen by each input. In case of the preemptive priority policy without considering a window scheme, we extend the approximation technique used by Chen and Guerin [1] to obtain more accurate results. Moreover, we also propose newly a window scheme that is appropriate for the preemptive priority switching system in view of implementation and operation. It can improve the total system throughput and delay performance of low priority packets. We also analyze this window scheme using an equivalent queueing system and compare the performance results with that without the window scheme. Numerical results are compared with simulations.

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Performance Evaluation of a High-Speed LAN using a Dual Mode Switching Access Protocol (이중 모드 스윗칭 억세스 프로토콜을 이용한 고속 근거리 통신망의 성능평가)

  • 주기호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.10
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    • pp.2620-2633
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    • 1996
  • In this paper, a new high-speed local area network using a dual mode switching access (DMSA) protocol implemented on a dual unidirectional bus is described. By utilizing the implicit positionalordering of stations on a unidirectional bus, the proposed system switches between random access mode and the token access model withoug unnecessary delay. Therefore, unlike other hybrid systems such as Buzz-net and Z-net, DMSA does not show a rapid degradation in performance as the load increases. We obtain the average channel utilization and the average access delay by using a simplified analytic model. The numerical results obtained via analysis are compared to the simulation resuls for a partial validation of the approximate model. The performance characteristics of DMSA are superior delay-throughput characteristics at light and medium loads, compared to compared to other LAN systems, and the capability of providing a single active station with full capabity of the channel.

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A Study on the PWN Inverter for the Design of UPS (무정전 전원(UPS)설계를 위한 PWN 인버터에 관한 연구)

  • 이성백;구용회;이종규
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.2 no.2
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    • pp.59-63
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    • 1988
  • In a fixed AC power source the PWM techniques were used to vary the voltage and the fundamental frequency. The conventional PWM techniques due to the problem of commutation number and filter size have been studied the PWM output waveforms which applied the motor drive. However in this paper, the carrier frequency with sinusoidal PWM waveform is modulated from 10(KHz) to 45(KHz) using termination devices with high - speed switching capacity and applying LPF(Low Pass Filter) with small capacity to output of inverter and the PAM(Pulse Amplitude Modulation)is obtained. Considering the property of the speed and the control, the sinusoidal PWM control circuit was composed of the microprocessor and analog circuit. In experment result, the system properties are study on the sinusoidal voltage waveform with modulation index changing from 0.6 to 1.0.

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