• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.69-76
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• 2000

A dual-modulus prescaler divides the input signal by one of the moduli according to the control signal. In this paper, a new fast dual-modulus prescaler is proposed. The proposed prescaler has a ratioed-NOR structure different from a conventional ratioed-NAND structure. The proposed one can operate at a higher speed by using parallely connected NMOSs instead of using series-connected ones. HSPICE simulation results using HYUNDAI 0.65(m 2-poly 2-metal CMOS process parameters show that the maximum operating frequency of the proposed dual-modulus prescaler is 2.8㎓ with power consumption of 40.7㎽ at 5V supply voltage at $25^{\circ}C$. The proposed dual-modulus prescaler can be utilized for the frequency-synthesis in cellular radio front-ends.

• Electronics and Telecommunications Trends
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• v.19 no.2 s.86
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• pp.138-146
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• 2004

시스템 연결에 사용되는 프로토콜이 고속, 직렬화 됨에 따라 CDR이 내장된 SERDES 칩의 사용이 늘어나고 있다. 이에 Xilinx 나 Altera 사 등 FPGA 업체들이 SERDES를 FPGA 내장시킨 제품을 출시하기 시작하였다. 이러한 SERDES 임베디드 FPGA는 PCB 설계의 단순화와 신호무결성의 큰 이점이 있다. 본 고에서는 Altera 사의 SERDES 임베디드 FPGA, Stratix-GX 디바이스의 기가비트 트랜시버 ALTGXB 블록의 테스트에 관해 살펴본다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.119-127
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• 2012

This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.566-572
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• 2000

In the receiver of optical communication systems, a demultiplexer converts to a single data stream with a highbit rate into several parallel data streams with a low bit rate. In this paper, we design a 1:4 demultiplexer using SiGe HBT with emitter size of 2x8um² The operation speed is 10Gbps, the rise and fall times of 20-80% are37ps and 36ps, respectively and the dissipation of power is 1.40W.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.761-764
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• 2007

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and πace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.72-73
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• 2007

기존의 공정자동화 설비에서는 센서를 통하여 계측된 데이터들이 4-20mA의 아날로그 신호를 통하여 제어기와 컴퓨터들로 전송되었다. 이러한 아날로그 신호 전송 방식에서는 제어 시스템의 구조가 복잡해지고 설치에 많은 비용과 노력이 투입될 수밖에 없다. 이러한 문제점을 해소하기 위하여 기술 선진국에서는 필드 장비들 간에 고속의 직렬 통신을 통하여 제어 및 자동화 관련 디지털 데이터의 전송을 실시간으로 지원하는 필드버스 통신망을 개발하였으며, 1990년대 이후 공장 자동화, 공정 제어 및 발전 설비 등 각종 산업 설비에 필드버스를 매우 활발히 도입하고 있다. Foundation Fieldbus 모듈은 공정제어 시스템예서 사용되는 센서, 제어기, PLC, 밸브, 구동기, 스위치 등의 모든 필드 장비에 바로 탑재되어 Foundation Fieldbus의 통신 기능을 제공하는 통신 부품으로 첨단의 공정자동화 시스템을 구축하기 위하여 반드시 확보되어야 할 핵심기술이다. 본 연구를 통해 제작된 Foundation Fieldbus 모듈은 기존의 센서제품을 FF기반의 지능형 센서로 바로 전환할 수 있는 핵심부품이다.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.499-500
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• 2008

기존 칩들 사이에 사용되는 인터페이스는 많은 선을 사용하여 EMI문제를 발생시키고 PCB에 많은 중간을 차지한다. 이를 해결하기 위하여 개발된 UniPro는 적은 선으로 빠른 통신속도를 지원하며 저전력 통신을 위하여 D-PHY와 함께 사용된다. 본 논문에서는 MIPI 규격의 UniPro를 설계하였다. 설계된 UniPro는 4개의 데이터 레인과 1개의 클럭 레인으로 구성하여 디바이스 사이의 데이터 및 제어신호를 전송 가능하다. 또한 낮은 전력소모를 위하여 전원 관리 장치를 추가하였으며 수신한 데이터의 에러검출이 가능하도록 설계하여 신뢰도를 높였다. 설계된 인터페이스는 5,160 Gate크기이며 속도는 98MHz이다.

• Journal of Biomedical Engineering Research
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• v.7 no.2
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• pp.139-146
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• 1986

Pulsed ultrasonic Doppler system is a useful diagnostic instrument to measure blood-flow-velocity, velocity profile, and volume-blood-flow. This system is more powerful compare with 2-dimensional B-scan tissue image. A system has been deve- loped and ii being evaluated using TMS 32010 DSP. We use this DSP for the purpose of real-time spectrum analyzer to obtain spectrogram in singlegate pulsed Doppler system and for the serial comb filter to cancel clutter and zero crossing counter to estimate Doppler mean frequency in multigate pulsed Doppler system. The Doppler shift of the backscattered signals is sensed in a phase detector. This Doppler signal corresponds to the mean velocity over a some region in space defined by the ultrasonic beam dimensions, transmitted pulse duration, and transducer ban(iwidth. Multi- gate pulsed Doppler system enable the transcutaneous and simultaneous assessment of the velocities in a number of adjacent sample volumes as a continuous function of time. A multigate pulsed Doppler system processing the information originating from presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.364-371
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• 2007

In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of ${\sim}0.84\;dB$ and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of ${\sim}200\;nsec$. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.