• Journal of Biomedical Engineering Research
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• v.22 no.4
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• pp.339-347
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• 2001

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• 전기의세계
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• v.53 no.6
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• pp.32-36
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• 2004

한국형 고속전철은 국책과제인 G7(선도기술개발사업) 고속전철기술개발사업의 일환으로 개발되었다. 이로 인해 우리의 독자적인 기술이 해외 선진국과 경쟁할 수 있는 능력을 보여 줌은 물론, 21세기 국가철도망 요소 중 가장 중요한 한국형 고속전철차량을 국내 기술로 구축할 수 있게 되어, 향후 수입 대체, 관련 산업기술 파급 및 수출 증대 등 효과가 클 것으로 기대된다. 특히 고속전철의 핵심이라고 할 수 있는 주요 전장품을 자체 개발하였으며 300km/h 주행 성공 및 지속적인 안정화 시험을 통해 그 성능을 입증해 보이고 있다. 본 글에서는 한국형 고속전철의 주요 전장품인 주 전력 변환장치, 보조전원장치, 견인전동기의 주요 성능 및 특징에 대해 설명하고자 한다.(중략)

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2365-2371
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• 1998

Discrete cosine transform (DCT) has wide applications in speech and image coding. In this paper, we propose a novel fast dCT scheme with the property of reduced multiplication stages and the smaller number of additions and multiplications. This exploits the symmetry property of the DCT kernel to decompose the N-point dCT to N/2 point, and can be generally applied recursively to $2^{m}$-point. The proposed algorithm has a structure that most of multiplications tend to be performed at final stage, and this reduces propagation of truncation error which could occur in the fixed-point computation. Also the minimization of the multiplication stages further decreases the error.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1112-1115
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• 2000

본 논문에서는 One-bit 변환을 기반으로 한 고속의 가변 블록 크기 움직임 예측 알고리즘을 제안한다. 제안된 방법은 블록 내의 평균값을 이용하여 8bit 화소값을 1bit로 변환한 후 움직임 예측을 수행한다. One-bit 변환을 통한 영상의 단순화는 움직임 추정의 계산적 부담을 감소시켜 빠른 탐색을 가능하게 한다. 그리고 블록 내의 움직임 정도를 미리 판별하여 이를 기반으로 한 적응적 탐색이 불필요한 탐색을 제거하고 움직임이 큰 블록에서는 정합과정을 심화시켜 보다 정확한 움직임 예측을 수행한다. 본 제안된 방식을 가지고 실험한 결과 한 프레임당 적은 수의 블록으로 고정된 크기의 블록을 가진 전역 탐색 블록 정합 알고리즘(full search block matching algorithm; FSBMA)보다 예측 에러를 적게 발생시켜 평균적으로 0.5dB 정도의 PSNR 개선을 가져왔다. 특히, 움직임이 많은 영상에서 뛰어난 효과를 나타냈다.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.45-55
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• 1997

In this paper, we propose a fast algorithm with adaptive thresholding for the wavelet transform (WT) based blocking artifact reduction. In the fast algorithm, all processings that are equivalent to the processing in WT domain of the first and second scale are performed in spatial domain. In the adaptive thresholding, the threshold values used to classify the block boundary are selected adaptively according to each input image by using the statistical properties of the WT of the coded signal at block boundary and at block center, which can be obtained in spatial domain. Experimental results showed that the proposed fast algorithm is about 10 times faster than the WT-based algorithm. It also was found that the postprocessing with proposed adaptive thresholding yields some PSNR improvement and better subjective quality over that with nonadaptive thresholding which has best performance at high compression ratios of a certain .image, even at low compression ratios.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1176-1179
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• 1998

• Proceedings of the KIEE Conference
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• 1979.08a
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• pp.73-75
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• 1979