• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.558-566
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• 2000

Object recognition is a challenging application for high-performance computing. Currently, the superscalar architecture dominates todays microprocessor marketplace. As more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the object recognition on the on-chip multiprocessor, which will be employed in general-purpose parallel machines. To obtain the performance characteristics of the microprocessor, a program-driven simulator and its programming environment were developed. The simulation results showed that the on-chip multiprocessor can exploit thread level parallelisms effectively and offer a promising architecture for the object recognition application.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.722-726
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• 2010

The recent deployment of RIA (Rich Internet Application) is often involved with the complex JavaScript code, which leads to the announcement of high performance JavaScript engines for its efficient execution. And the Sunspider benchmark is being widely used for the performance evaluation of these JavaScript engines. In this paper, we compare the execution methods of three high-performance JavaScript engines, Mozilla TraceMonkey, Google V8, and Apple SquirrelFish Extreme, and measure their performances using the SunSpider benchmark. We also evaluate the pros and cons of each engine, based on its execution method and the code characteristics of the SunSpider benchmarks.

• Journal of the Korean Chemical Society
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• v.25 no.1
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• pp.30-37
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• 1981

A simple micro-sampling system is described which facilitates isolation and concentration of complex organic constituents into three fractions of different volatilities. The method involves the headspace trapping of very volatile components from a complex matrix onto a porous polymer, Tenax GC, followed by the solvent elution of the matrix and the subsequent fractions of the eluate into volatile and less-volatile fractions. The headspace and the volatile fractions are then analyzed by high-resolution capillary gas chromatography. The less-volatile fraction is analyzed by high-performance liquid chromatography. Experimental details and the results obtained using tobacco leaves as a complex organic matrix are presented.

• Journal of KIISE:Information Networking
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• v.28 no.1
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• pp.22-36
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• 2001

WWW의 급격한 발전은 몇몇 웹 서버에 큰 과부하를 가져오게 하였다. 이로 인해 고성능 웹서버의 구축이 필요하게 되었는데 그중 프로세스의 오버헤드를 줄이기 위해 도입된 멀티 쓰레드 기법을 이용한 병행 웹 서버들이 많이 이용되게 되었다. 일반적으로 멀티 쓰레드 기법을 이용하는 웹 서버의 구조는 요구 기반 웹 서버 작업 기반 웹 서버 Thread Pool 구조 웹 서버 등으로 나눌수 있다. 본 논문에서는 이런 웹 서버들을 리눅스가 탑재되어 있는 다중 처리기상에 구현하였으며 다양한 환경하에서 성능을 비교 분석하였다 각각의 웹 서버들은 Pthread 라이브러리와 Socket 라이브러리를 이용하여 구현하였으며 여러 파라미터-CPU 개수 CGI 비율, 웹 서버구조, 파일크기 부하량 등-를 조절하면서 실험하였다 실험 결과 분석에 의하면 요구 기반 웹 서버에서는 하나의 CPU에서 수행이 되는 쓰레드의 개수가 많게 되면 성능이 저하되는 것을 볼 수 있었고 작업 기반 웹 서버에서는 단계사이의 불균형으로 인하여 큐에서의 대기 시간이 누적되면 성능이 저하되는 것을 볼수 있었다,. Thread Pool 구조의 웹서버는 쓰레드의 개수가 조절되고 큐에서의 대기 시간 또한 없앰으로 해서 다른 웹 서버에 비해 좋은 성능을 보임을 알 수 있었다. 이와 같은 실험 결과는 다중 처리기를 이용한 고성능 웹 서버를 구축하는데 있어서 이용될 수 있을 것이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• Korean Journal of Optics and Photonics
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• v.30 no.5
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• pp.193-196
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• 2019

The design and control of thermal flow is important for the operation of high-power laser diodes (LDs). It is necessary to analyze and improve the thermal bottleneck near the active layer of an LD. As the error in prediction of the thermal resistance of an LD is large, typically due to the hyperbolic increase and saturation to linear increase of the thermal resistance as a function of thickness, it is helpful to use a simple, modified divergence model for the improvement and optimization of thermal resistance. The characteristics of LDs are described quite well, in that the values for simulated thermal resistance curves and the thermal cross section followed are almost the same as the values from the model function. Also, the thermal-cross-section curve obtained by differentiating the thermal resistance is good for identifying thermal bottlenecks intuitively, and is also fitted quite well by the model proposed for both a typical LD structure and an improved LD with thin capping and high thermal conductivity.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.2
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• pp.60-70
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• 2002

최근 고성능/고집적 RF 소자 및 시스템들의 경박 단소화 추세에 따라 RF 무선 통신 분야에도 초소형미세 가공 기술인 MEMS 기술이 크게 주목받고 있다. 이에 본 고에서는 RF 부품 및 시스템을 MEMS 기술로서 실장하는 RF MEMS 패키지 기술에 대하여 간단히 살펴보았다. 우선, 실리콘 기반의 MEMS 패키지가 우수한 열 전달 특성과 저 손실의 고주파특성으로 인해 RF 시스템의 실장에 매우 적합함을 확인하였다. 또한, MEMS 기술을 이용함으로써 RF회로와 패키지 제작 공정이 동시에 이루어질 수 있도록 하는 일괄터리공정에 대하여 소개하였다.

• Broadcasting and Media Magazine
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• v.2 no.3
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• pp.40-48
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• 1997

네트워크 가상현실 시스템은 먼 거리에 떨어진 사용자들 사이에 일관성 있는 가상 세계를 제공하며, 군사, 오락, 건축 등 여러 부분에 응용되고 있다. 본 논문에서는 그 동안 고성능 그래픽 워크스테이션 환경에서 중심적으로 연구되어 왔던 네트워크 가상현실 시스템을 가장보편적인 플랫폼인 PC환경에서 구현할 때 생기는 3차원 그래픽 처리 성능의 문제, 네트워크 대역폭과 전송지연의 문제 등 여러 문제점들과 이에 대한 해결책들을 제시하고 건축 시뮬레이션을 응용으로 삼아 복수 사용자 가상현실을 구현하였다.