• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.50-51
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• 2012

본 논문에서는 기존의 홀로그램 행(열)단위 병렬 연산 방식의 고성능 홀로그램 생성기의 하드웨어 자원 량을 효율적으로 사용하기 위해 공통항을 늘려 자원 량을 줄일 수 있는 구조를 제안한다. 하나의 2D 블록의 행과 열에 해당하는 좌표 항을 연산 후 좌표 항을 이용하여 각 블록의 화소 값을 계산한다. 이전 연구에서의 메모리 접근 량을 줄일 뿐만 아니라 이전 연구에 비하여 조합회로는 45% DSP 블록은 90% 감소하여 하드웨어 자원을 효율적으로 사용할 수 있다.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• Defense and Technology
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• no.8 s.174
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• pp.44-51
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• 1993

F-5 성능개량의 근본적인 배경은 경제성입니다. F-16 한대 도입할 가격이면 대략 10대의 F-5 성능개량이 가능하므로 비용 대 효과 측면에서 많은 국가들이 매력을 느끼고 있습니다 또한 선도 훈련기로서의 필요성이 전투기.성능이 급격히 높아짐에 따라, 성능개량되는 F-5 수준의 항공기로 예비훈련을 함으로써, 고성능 전투기의 비전력화 훈련소요를 상당부분 대체할수 있습니다

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.533-536
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• 2016

This paper describes a vibrational energy harvesting circuit with MPPT control. A high-performance AC-DC converter of which the efficiency is improved by using body-bias technique and bulk-driven technique is proposed and applied for the vibrational energy harvesting circuit design. MPPT (Maximum Power Point Tracking) control function is implemented using the linear relationship between the open-circuit voltage of a vibrational device and its MPP voltage. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a vibrational device, makes the reference voltages using sampled voltage and delivers the maximum available power to load. The proposed circuit is designed with a $0.35{\mu}m$ CMOS process, and the chip area is $1.21mm{\times}0.98mm$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.30-41
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• 2023

With the aggressive down-scaling of advanced integrated circuits (ICs), electronic packages have become the bottleneck of both reliability and performance of whole electronic systems. In order to resolve the reliability issues, Institute of Electrical and Electronics Engineers (IEEE) laid down a roadmap on fault detection and diagnosis (FDD), thrusting the digital twin: a combination of reliability physics and artificial intelligence (AI). In this paper, we especially review research works regarding the signal-based FDD approaches on the electronic packages. We also discuss the research trend of FDD utilizing AI techniques.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.48-61
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• 2017

An IaaS service of a cloud computing environment makes itself attractive for running large scale parallel application thanks to its innate characteristics that a user can utilize a desired number of high performance virtual machines without maintenance cost. The total execution time of a parallel application on a high performance computing environment depends on a task scheduling algorithm. Most studies on task scheduling algorithms on cloud computing environment try to reduce a user cost, and studies on task scheduling algorithms that try to reduce total execution time are rarely carried out. In this paper, we propose a task scheduling algorithm called an HAGD and a performance enhancement method called a group task duplication method of which the HAGD utilizes. The group task duplication method simplifies previous task duplication method, and the HAGD uses the group task duplication method or a task insertion method according to the characteristics of a computing environment and an application. We found that the proposed algorithm provides superior performance regardless of the characteristics in terms of normalized total execution time through performance evaluations.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2551-2553
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• 2000

고속 신호처리 및 실시간 제어 분야에 적합한 제어성능을 발휘하기 위해서는 신호처리전용 마이크로프로세서인 DSP(Digital Signal Processor)를 이용한 제어용 보드가 널리 활용되고 있다. 본 연구를 통하여 전기도금용 전원장치의 고성능화를 위하여 DSP제어용 보드를 개발하였으며, 전체구성은 고속 신호처리를 위한 메인 마이크로프로세서로서 경제성과 응용범위가 넓은 TMS320C32 DSP CHIP, Wait없는 프로그램 및 데이터 처리를 위한 고속 SRAM, 외부 디지털 입출력을 위한 인터페이스 회로, 아나로그 입출력 회로 및 PC 혹은 다른 마이크로컴퓨터와의 통신을 위한 직렬 통신 회로 등으로 구성하였다. 개발된 DSP 보드는 시제품 제작을 완료하여 그 성능 및 신뢰성을 검증하였으며, 전기도금장치의 고성능 제어처리를 위하여 채용하여 상품화 개발을 완료하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.769-776
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• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.53-61
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• 2006

This paper is proposed adaptive fuzzy-neuro controller for high performance of induction motor drive. The design of this algorithm based on fuzzy-neural network controller that is implemented using fuzzy control and neural network. This controller uses fuzzy nile as training patterns of a neural network. Also, this controller uses the back-propagation method to adjust the weights between the neurons of neural network in order to minimize the error between the command output and actual output. A model reference adaptive scheme is proposed in which the adaptation mechanism is executed by fuzzy logic based on the error and change of error measured between the motor speed and output of a reference model. The control performance of the adaptive fuzzy-neuro controller is evaluated by analysis for various operating conditions. The results of experiment prove that the proposed control system has strong high performance and robustness to parameter variation, and steady-state accuracy and transient response.